Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T14,T73

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	21739305	5741	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	21739305	228447	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	21739305	8865247	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	21739305	228457	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	21739305	5741	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	21739305	228447	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	21739305	8865247	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	21739305	228457	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21739305	5741	0	0
T2	9593	8	0	0
T3	2915	0	0	0
T4	709	0	0	0
T5	2338	1	0	0
T6	5579	0	0	0
T7	273898	86	0	0
T8	3323	0	0	0
T9	4258	0	0	0
T10	4437	0	0	0
T14	0	79	0	0
T26	0	24	0	0
T30	0	12	0	0
T33	1685	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	4	0	0
T77	0	17	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21739305	228447	0	0
T2	9593	133	0	0
T3	2915	0	0	0
T4	709	0	0	0
T5	2338	13	0	0
T6	5579	0	0	0
T7	273898	1658	0	0
T8	3323	0	0	0
T9	4258	0	0	0
T10	4437	0	0	0
T14	0	3841	0	0
T26	0	584	0	0
T30	0	493	0	0
T33	1685	0	0	0
T74	0	12	0	0
T75	0	12	0	0
T76	0	94	0	0
T77	0	318	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21739305	8865247	0	0
T2	9593	3709	0	0
T3	2915	0	0	0
T4	709	0	0	0
T5	2338	1432	0	0
T6	5579	0	0	0
T7	273898	118821	0	0
T8	3323	0	0	0
T9	4258	2402	0	0
T10	4437	0	0	0
T14	0	225185	0	0
T26	0	15035	0	0
T27	0	9244	0	0
T30	0	50655	0	0
T33	1685	0	0	0
T74	0	1298	0	0
T78	0	715	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21739305	228457	0	0
T2	9593	133	0	0
T3	2915	0	0	0
T4	709	0	0	0
T5	2338	13	0	0
T6	5579	0	0	0
T7	273898	1658	0	0
T8	3323	0	0	0
T9	4258	0	0	0
T10	4437	0	0	0
T14	0	3841	0	0
T26	0	584	0	0
T30	0	493	0	0
T33	1685	0	0	0
T74	0	12	0	0
T75	0	12	0	0
T76	0	94	0	0
T77	0	318	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21739305	5741	0	0
T2	9593	8	0	0
T3	2915	0	0	0
T4	709	0	0	0
T5	2338	1	0	0
T6	5579	0	0	0
T7	273898	86	0	0
T8	3323	0	0	0
T9	4258	0	0	0
T10	4437	0	0	0
T14	0	79	0	0
T26	0	24	0	0
T30	0	12	0	0
T33	1685	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	4	0	0
T77	0	17	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21739305	228447	0	0
T2	9593	133	0	0
T3	2915	0	0	0
T4	709	0	0	0
T5	2338	13	0	0
T6	5579	0	0	0
T7	273898	1658	0	0
T8	3323	0	0	0
T9	4258	0	0	0
T10	4437	0	0	0
T14	0	3841	0	0
T26	0	584	0	0
T30	0	493	0	0
T33	1685	0	0	0
T74	0	12	0	0
T75	0	12	0	0
T76	0	94	0	0
T77	0	318	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21739305	8865247	0	0
T2	9593	3709	0	0
T3	2915	0	0	0
T4	709	0	0	0
T5	2338	1432	0	0
T6	5579	0	0	0
T7	273898	118821	0	0
T8	3323	0	0	0
T9	4258	2402	0	0
T10	4437	0	0	0
T14	0	225185	0	0
T26	0	15035	0	0
T27	0	9244	0	0
T30	0	50655	0	0
T33	1685	0	0	0
T74	0	1298	0	0
T78	0	715	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21739305	228457	0	0
T2	9593	133	0	0
T3	2915	0	0	0
T4	709	0	0	0
T5	2338	13	0	0
T6	5579	0	0	0
T7	273898	1658	0	0
T8	3323	0	0	0
T9	4258	0	0	0
T10	4437	0	0	0
T14	0	3841	0	0
T26	0	584	0	0
T30	0	493	0	0
T33	1685	0	0	0
T74	0	12	0	0
T75	0	12	0	0
T76	0	94	0	0
T77	0	318	0	0