Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	22309100	14133	0	0
intr_enable_rd_A	22309100	32184	0	0
reset_en_rd_A	22309100	1788	0	0
reset_en_regwen_rd_A	22309100	1652	0	0
wake_info_capture_dis_rd_A	22309100	1685	0	0
wakeup_en_rd_A	22309100	2425	0	0
wakeup_en_regwen_rd_A	22309100	1658	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22309100	14133	0	0
T7	273898	4	0	0
T8	3323	0	0	0
T9	4258	0	0	0
T10	4437	0	0	0
T11	15279	0	0	0
T14	520556	32	0	0
T21	0	19	0	0
T22	6309	0	0	0
T33	1685	0	0	0
T39	0	12	0	0
T74	1773	0	0	0
T78	2123	0	0	0
T80	0	29	0	0
T81	0	13	0	0
T82	0	2	0	0
T140	0	20	0	0
T141	0	11	0	0
T142	0	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22309100	32184	0	0
T2	9593	20	0	0
T3	2915	32	0	0
T4	709	0	0	0
T5	2338	0	0	0
T6	5579	0	0	0
T7	273898	3061	0	0
T8	3323	0	0	0
T9	4258	59	0	0
T10	4437	0	0	0
T26	0	164	0	0
T33	1685	0	0	0
T73	0	11	0	0
T75	0	10	0	0
T77	0	165	0	0
T78	0	48	0	0
T143	0	5	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22309100	1788	0	0
T7	273898	5	0	0
T8	3323	0	0	0
T9	4258	0	0	0
T10	4437	0	0	0
T11	15279	0	0	0
T14	520556	0	0	0
T22	6309	0	0	0
T33	1685	0	0	0
T41	0	72	0	0
T63	0	14	0	0
T74	1773	0	0	0
T78	2123	0	0	0
T81	0	21	0	0
T88	0	17	0	0
T97	0	6	0	0
T144	0	3	0	0
T145	0	9	0	0
T146	0	1	0	0
T147	0	418	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22309100	1652	0	0
T7	273898	6	0	0
T8	3323	0	0	0
T9	4258	0	0	0
T10	4437	0	0	0
T11	15279	0	0	0
T14	520556	0	0	0
T22	6309	0	0	0
T33	1685	0	0	0
T41	0	41	0	0
T63	0	16	0	0
T74	1773	0	0	0
T78	2123	0	0	0
T81	0	13	0	0
T88	0	22	0	0
T97	0	4	0	0
T118	0	83	0	0
T144	0	4	0	0
T145	0	7	0	0
T147	0	456	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22309100	1685	0	0
T7	273898	2	0	0
T8	3323	0	0	0
T9	4258	0	0	0
T10	4437	0	0	0
T11	15279	0	0	0
T14	520556	0	0	0
T22	6309	0	0	0
T33	1685	0	0	0
T41	0	39	0	0
T63	0	16	0	0
T74	1773	0	0	0
T78	2123	0	0	0
T81	0	6	0	0
T88	0	20	0	0
T97	0	5	0	0
T144	0	2	0	0
T145	0	4	0	0
T146	0	6	0	0
T147	0	428	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22309100	2425	0	0
T7	273898	6	0	0
T8	3323	0	0	0
T9	4258	0	0	0
T10	4437	0	0	0
T11	15279	0	0	0
T14	520556	0	0	0
T22	6309	0	0	0
T33	1685	0	0	0
T41	0	138	0	0
T63	0	16	0	0
T74	1773	0	0	0
T78	2123	0	0	0
T81	0	14	0	0
T88	0	6	0	0
T118	0	133	0	0
T132	0	10	0	0
T144	0	9	0	0
T145	0	8	0	0
T147	0	455	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22309100	1658	0	0
T7	273898	4	0	0
T8	3323	0	0	0
T9	4258	0	0	0
T10	4437	0	0	0
T11	15279	0	0	0
T14	520556	0	0	0
T22	6309	0	0	0
T33	1685	0	0	0
T41	0	38	0	0
T63	0	16	0	0
T74	1773	0	0	0
T78	2123	0	0	0
T81	0	12	0	0
T82	0	8	0	0
T88	0	8	0	0
T97	0	4	0	0
T144	0	9	0	0
T145	0	4	0	0
T147	0	439	0	0