Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	21739305	54625	0	0
RomAllowCheckGoodState_A	21739305	54676	0	0
RomBlockActiveState_A	21739305	28762	0	0
RomBlockCheckGoodState_A	21739305	393405	0	0
RomIntgChkDisFalse_A	21739305	21165790	0	0
RomIntgChkDisTrue_A	21739305	84424	0	0
RstreqChkEsctimeout_A	21739305	4014	0	0
RstreqChkFsmterm_A	21739305	160	0	0
RstreqChkGlbesc_A	21739305	4015	0	0
RstreqChkMainpd_A	21739305	878700	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21739305	54625	0	0
T1	1608	7	0	0
T2	9593	38	0	0
T3	2915	13	0	0
T4	709	6	0	0
T5	2338	3	0	0
T6	5579	12	0	0
T7	273898	1141	0	0
T8	3323	6	0	0
T9	4258	17	0	0
T10	4437	8	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21739305	54676	0	0
T1	1608	7	0	0
T2	9593	38	0	0
T3	2915	13	0	0
T4	709	6	0	0
T5	2338	3	0	0
T6	5579	13	0	0
T7	273898	1141	0	0
T8	3323	6	0	0
T9	4258	17	0	0
T10	4437	8	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21739305	28762	0	0
T1	1608	260	0	0
T2	9593	0	0	0
T3	2915	0	0	0
T4	709	0	0	0
T5	2338	0	0	0
T6	5579	0	0	0
T7	273898	0	0	0
T8	3323	0	0	0
T9	4258	0	0	0
T10	4437	814	0	0
T22	0	1240	0	0
T25	0	49	0	0
T29	0	758	0	0
T77	0	3	0	0
T148	0	1012	0	0
T149	0	14	0	0
T150	0	22	0	0
T151	0	26	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21739305	393405	0	0
T1	1608	65	0	0
T2	9593	460	0	0
T3	2915	0	0	0
T4	709	0	0	0
T5	2338	0	0	0
T6	5579	0	0	0
T7	273898	3911	0	0
T8	3323	0	0	0
T9	4258	0	0	0
T10	4437	843	0	0
T14	0	3626	0	0
T22	0	1093	0	0
T26	0	1449	0	0
T29	0	819	0	0
T30	0	758	0	0
T76	0	161	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21739305	21165790	0	0
T1	1608	1459	0	0
T2	9593	9426	0	0
T3	2915	2834	0	0
T4	709	563	0	0
T5	2338	2284	0	0
T6	5579	4688	0	0
T7	273898	265116	0	0
T8	3323	2882	0	0
T9	4258	4178	0	0
T10	4437	3218	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21739305	84424	0	0
T1	1608	92	0	0
T2	9593	0	0	0
T3	2915	0	0	0
T4	709	0	0	0
T5	2338	0	0	0
T6	5579	0	0	0
T7	273898	0	0	0
T8	3323	0	0	0
T9	4258	0	0	0
T10	4437	1137	0	0
T22	0	225	0	0
T25	0	134	0	0
T29	0	89	0	0
T77	0	114	0	0
T89	0	857	0	0
T148	0	1217	0	0
T149	0	564	0	0
T152	0	269	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21739305	4014	0	0
T1	1608	1	0	0
T2	9593	0	0	0
T3	2915	6	0	0
T4	709	3	0	0
T5	2338	0	0	0
T6	5579	4	0	0
T7	273898	83	0	0
T8	3323	5	0	0
T9	4258	0	0	0
T10	4437	4	0	0
T14	0	71	0	0
T22	0	3	0	0
T33	0	4	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21739305	160	0	0
T12	15317	0	0	0
T18	9747	20	0	0
T19	0	40	0	0
T20	0	20	0	0
T23	0	40	0	0
T24	0	40	0	0
T25	1198	0	0	0
T26	26639	0	0	0
T27	16668	0	0	0
T28	2029	0	0	0
T29	5036	0	0	0
T30	109120	0	0	0
T31	8250	0	0	0
T32	4436	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21739305	4015	0	0
T1	1608	1	0	0
T2	9593	0	0	0
T3	2915	6	0	0
T4	709	3	0	0
T5	2338	0	0	0
T6	5579	4	0	0
T7	273898	83	0	0
T8	3323	5	0	0
T9	4258	0	0	0
T10	4437	4	0	0
T14	0	71	0	0
T22	0	3	0	0
T33	0	4	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21739305	878700	0	0
T1	1608	192	0	0
T2	9593	218	0	0
T3	2915	395	0	0
T4	709	26	0	0
T5	2338	0	0	0
T6	5579	123	0	0
T7	273898	4140	0	0
T8	3323	0	0	0
T9	4258	0	0	0
T10	4437	973	0	0
T14	0	16896	0	0
T22	0	2300	0	0
T25	0	28	0	0