Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7061 |
1 |
|
|
T2 |
8 |
|
T7 |
5 |
|
T32 |
15 |
auto[1] |
18901 |
1 |
|
|
T1 |
18 |
|
T2 |
8 |
|
T3 |
50 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11800 |
1 |
|
|
T1 |
9 |
|
T2 |
6 |
|
T3 |
28 |
auto[1] |
14162 |
1 |
|
|
T1 |
9 |
|
T2 |
10 |
|
T3 |
22 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12256 |
1 |
|
|
T1 |
6 |
|
T2 |
8 |
|
T3 |
23 |
auto[1] |
13706 |
1 |
|
|
T1 |
12 |
|
T2 |
8 |
|
T3 |
27 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1587 |
1 |
|
|
T2 |
3 |
|
T7 |
3 |
|
T32 |
5 |
auto[0] |
auto[0] |
auto[1] |
1647 |
1 |
|
|
T7 |
1 |
|
T32 |
2 |
|
T22 |
16 |
auto[0] |
auto[1] |
auto[0] |
4465 |
1 |
|
|
T1 |
4 |
|
T2 |
1 |
|
T3 |
15 |
auto[0] |
auto[1] |
auto[1] |
4101 |
1 |
|
|
T1 |
5 |
|
T2 |
2 |
|
T3 |
13 |
auto[1] |
auto[0] |
auto[0] |
1614 |
1 |
|
|
T2 |
1 |
|
T7 |
1 |
|
T32 |
2 |
auto[1] |
auto[0] |
auto[1] |
2213 |
1 |
|
|
T2 |
4 |
|
T32 |
6 |
|
T22 |
22 |
auto[1] |
auto[1] |
auto[0] |
4590 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T3 |
8 |
auto[1] |
auto[1] |
auto[1] |
5745 |
1 |
|
|
T1 |
7 |
|
T2 |
2 |
|
T3 |
14 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7061 |
1 |
|
|
T2 |
8 |
|
T7 |
5 |
|
T32 |
15 |
auto[1] |
18901 |
1 |
|
|
T1 |
18 |
|
T2 |
8 |
|
T3 |
50 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11702 |
1 |
|
|
T1 |
10 |
|
T2 |
8 |
|
T3 |
21 |
auto[1] |
14260 |
1 |
|
|
T1 |
8 |
|
T2 |
8 |
|
T3 |
29 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12214 |
1 |
|
|
T1 |
8 |
|
T2 |
8 |
|
T3 |
24 |
auto[1] |
13748 |
1 |
|
|
T1 |
10 |
|
T2 |
8 |
|
T3 |
26 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1544 |
1 |
|
|
T2 |
2 |
|
T7 |
1 |
|
T32 |
3 |
auto[0] |
auto[0] |
auto[1] |
1716 |
1 |
|
|
T2 |
3 |
|
T7 |
2 |
|
T32 |
3 |
auto[0] |
auto[1] |
auto[0] |
4350 |
1 |
|
|
T1 |
3 |
|
T2 |
1 |
|
T3 |
12 |
auto[0] |
auto[1] |
auto[1] |
4092 |
1 |
|
|
T1 |
7 |
|
T2 |
2 |
|
T3 |
9 |
auto[1] |
auto[0] |
auto[0] |
1628 |
1 |
|
|
T2 |
2 |
|
T7 |
1 |
|
T32 |
4 |
auto[1] |
auto[0] |
auto[1] |
2173 |
1 |
|
|
T2 |
1 |
|
T7 |
1 |
|
T32 |
5 |
auto[1] |
auto[1] |
auto[0] |
4692 |
1 |
|
|
T1 |
5 |
|
T2 |
3 |
|
T3 |
12 |
auto[1] |
auto[1] |
auto[1] |
5767 |
1 |
|
|
T1 |
3 |
|
T2 |
2 |
|
T3 |
17 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7061 |
1 |
|
|
T2 |
8 |
|
T7 |
5 |
|
T32 |
15 |
auto[1] |
18901 |
1 |
|
|
T1 |
18 |
|
T2 |
8 |
|
T3 |
50 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11756 |
1 |
|
|
T1 |
11 |
|
T2 |
6 |
|
T3 |
22 |
auto[1] |
14206 |
1 |
|
|
T1 |
7 |
|
T2 |
10 |
|
T3 |
28 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12185 |
1 |
|
|
T1 |
10 |
|
T2 |
7 |
|
T3 |
24 |
auto[1] |
13777 |
1 |
|
|
T1 |
8 |
|
T2 |
9 |
|
T3 |
26 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1612 |
1 |
|
|
T2 |
2 |
|
T32 |
3 |
|
T22 |
15 |
auto[0] |
auto[0] |
auto[1] |
1676 |
1 |
|
|
T2 |
1 |
|
T7 |
1 |
|
T32 |
8 |
auto[0] |
auto[1] |
auto[0] |
4339 |
1 |
|
|
T1 |
7 |
|
T2 |
1 |
|
T3 |
13 |
auto[0] |
auto[1] |
auto[1] |
4129 |
1 |
|
|
T1 |
4 |
|
T2 |
2 |
|
T3 |
9 |
auto[1] |
auto[0] |
auto[0] |
1606 |
1 |
|
|
T2 |
1 |
|
T7 |
1 |
|
T22 |
17 |
auto[1] |
auto[0] |
auto[1] |
2167 |
1 |
|
|
T2 |
4 |
|
T7 |
3 |
|
T32 |
4 |
auto[1] |
auto[1] |
auto[0] |
4628 |
1 |
|
|
T1 |
3 |
|
T2 |
3 |
|
T3 |
11 |
auto[1] |
auto[1] |
auto[1] |
5805 |
1 |
|
|
T1 |
4 |
|
T2 |
2 |
|
T3 |
17 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7061 |
1 |
|
|
T2 |
8 |
|
T7 |
5 |
|
T32 |
15 |
auto[1] |
18901 |
1 |
|
|
T1 |
18 |
|
T2 |
8 |
|
T3 |
50 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11801 |
1 |
|
|
T1 |
10 |
|
T2 |
8 |
|
T3 |
24 |
auto[1] |
14161 |
1 |
|
|
T1 |
8 |
|
T2 |
8 |
|
T3 |
26 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12246 |
1 |
|
|
T1 |
5 |
|
T2 |
7 |
|
T3 |
28 |
auto[1] |
13716 |
1 |
|
|
T1 |
13 |
|
T2 |
9 |
|
T3 |
22 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1593 |
1 |
|
|
T2 |
3 |
|
T7 |
1 |
|
T32 |
4 |
auto[0] |
auto[0] |
auto[1] |
1687 |
1 |
|
|
T2 |
2 |
|
T32 |
6 |
|
T22 |
17 |
auto[0] |
auto[1] |
auto[0] |
4444 |
1 |
|
|
T1 |
3 |
|
T2 |
1 |
|
T3 |
15 |
auto[0] |
auto[1] |
auto[1] |
4077 |
1 |
|
|
T1 |
7 |
|
T2 |
2 |
|
T3 |
9 |
auto[1] |
auto[0] |
auto[0] |
1548 |
1 |
|
|
T2 |
2 |
|
T7 |
2 |
|
T32 |
2 |
auto[1] |
auto[0] |
auto[1] |
2233 |
1 |
|
|
T2 |
1 |
|
T7 |
2 |
|
T32 |
3 |
auto[1] |
auto[1] |
auto[0] |
4661 |
1 |
|
|
T1 |
2 |
|
T2 |
1 |
|
T3 |
13 |
auto[1] |
auto[1] |
auto[1] |
5719 |
1 |
|
|
T1 |
6 |
|
T2 |
4 |
|
T3 |
13 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7061 |
1 |
|
|
T2 |
8 |
|
T7 |
5 |
|
T32 |
15 |
auto[1] |
18901 |
1 |
|
|
T1 |
18 |
|
T2 |
8 |
|
T3 |
50 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11758 |
1 |
|
|
T1 |
10 |
|
T2 |
6 |
|
T3 |
22 |
auto[1] |
14204 |
1 |
|
|
T1 |
8 |
|
T2 |
10 |
|
T3 |
28 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12251 |
1 |
|
|
T1 |
9 |
|
T2 |
6 |
|
T3 |
26 |
auto[1] |
13711 |
1 |
|
|
T1 |
9 |
|
T2 |
10 |
|
T3 |
24 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1626 |
1 |
|
|
T7 |
1 |
|
T32 |
4 |
|
T22 |
21 |
auto[0] |
auto[0] |
auto[1] |
1635 |
1 |
|
|
T2 |
2 |
|
T32 |
3 |
|
T22 |
15 |
auto[0] |
auto[1] |
auto[0] |
4384 |
1 |
|
|
T1 |
7 |
|
T2 |
2 |
|
T3 |
15 |
auto[0] |
auto[1] |
auto[1] |
4113 |
1 |
|
|
T1 |
3 |
|
T2 |
2 |
|
T3 |
7 |
auto[1] |
auto[0] |
auto[0] |
1655 |
1 |
|
|
T2 |
3 |
|
T7 |
2 |
|
T32 |
1 |
auto[1] |
auto[0] |
auto[1] |
2145 |
1 |
|
|
T2 |
3 |
|
T7 |
2 |
|
T32 |
7 |
auto[1] |
auto[1] |
auto[0] |
4586 |
1 |
|
|
T1 |
2 |
|
T2 |
1 |
|
T3 |
11 |
auto[1] |
auto[1] |
auto[1] |
5818 |
1 |
|
|
T1 |
6 |
|
T2 |
3 |
|
T3 |
17 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7061 |
1 |
|
|
T2 |
8 |
|
T7 |
5 |
|
T32 |
15 |
auto[1] |
18901 |
1 |
|
|
T1 |
18 |
|
T2 |
8 |
|
T3 |
50 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11776 |
1 |
|
|
T1 |
10 |
|
T2 |
6 |
|
T3 |
25 |
auto[1] |
14186 |
1 |
|
|
T1 |
8 |
|
T2 |
10 |
|
T3 |
25 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12304 |
1 |
|
|
T1 |
10 |
|
T2 |
4 |
|
T3 |
27 |
auto[1] |
13658 |
1 |
|
|
T1 |
8 |
|
T2 |
12 |
|
T3 |
23 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1630 |
1 |
|
|
T2 |
2 |
|
T7 |
2 |
|
T32 |
4 |
auto[0] |
auto[0] |
auto[1] |
1639 |
1 |
|
|
T2 |
2 |
|
T7 |
1 |
|
T32 |
5 |
auto[0] |
auto[1] |
auto[0] |
4417 |
1 |
|
|
T1 |
8 |
|
T3 |
13 |
|
T7 |
1 |
auto[0] |
auto[1] |
auto[1] |
4090 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
12 |
auto[1] |
auto[0] |
auto[0] |
1614 |
1 |
|
|
T2 |
1 |
|
T7 |
1 |
|
T32 |
4 |
auto[1] |
auto[0] |
auto[1] |
2178 |
1 |
|
|
T2 |
3 |
|
T7 |
1 |
|
T32 |
2 |
auto[1] |
auto[1] |
auto[0] |
4643 |
1 |
|
|
T1 |
2 |
|
T2 |
1 |
|
T3 |
14 |
auto[1] |
auto[1] |
auto[1] |
5751 |
1 |
|
|
T1 |
6 |
|
T2 |
5 |
|
T3 |
11 |