Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	484595	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

183843

1

T1

70

T2

42

T3

206

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	346822	1			T1	157		T2	86		T3	410
values[0x0]	160665	1			T1	83		T2	52		T3	224
values[0x1]	160951	1			T1	81		T2	62		T3	228

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	383772	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

284666

1

T1

124

T2

68

T3

349

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1816	1			T3	7		T4	2		T6	2
valid_sources[0x01]	2352	1			T3	1		T4	2		T32	10
valid_sources[0x02]	1769	1			T3	2		T22	35		T25	5
valid_sources[0x03]	3202	1			T4	2		T32	6		T22	34
valid_sources[0x04]	1833	1			T3	4		T22	36		T25	1
valid_sources[0x05]	3750	1			T4	3		T15	2		T32	4
valid_sources[0x06]	1793	1			T4	3		T7	3		T32	3
valid_sources[0x07]	2347	1			T3	4		T6	1		T32	3
valid_sources[0x08]	2236	1			T3	2		T15	2		T22	42
valid_sources[0x09]	2734	1			T15	1		T16	16		T22	37
valid_sources[0x0a]	1773	1			T3	8		T22	47		T25	3
valid_sources[0x0b]	2706	1			T3	3		T6	2		T32	16
valid_sources[0x0c]	2348	1			T6	1		T7	1		T32	2
valid_sources[0x0d]	2068	1			T3	4		T7	2		T22	38
valid_sources[0x0e]	3882	1			T15	2		T22	40		T25	9
valid_sources[0x0f]	1900	1			T4	1		T22	35		T25	5
valid_sources[0x10]	4190	1			T3	1		T22	36		T25	1
valid_sources[0x11]	1648	1			T3	8		T15	1		T32	3
valid_sources[0x12]	2472	1			T3	9		T4	5		T6	2
valid_sources[0x13]	2132	1			T16	18		T32	13		T22	39
valid_sources[0x14]	1939	1			T22	33		T25	4		T23	17
valid_sources[0x15]	2009	1			T3	1		T4	1		T7	5
valid_sources[0x16]	3858	1			T7	1		T15	1		T22	32
valid_sources[0x17]	1851	1			T3	5		T7	3		T32	7
valid_sources[0x18]	2755	1			T6	1		T7	1		T32	8
valid_sources[0x19]	2767	1			T3	1		T6	1		T7	2
valid_sources[0x1a]	2591	1			T3	2		T6	1		T7	3
valid_sources[0x1b]	2294	1			T3	7		T22	38		T25	3
valid_sources[0x1c]	2097	1			T3	5		T32	9		T22	47
valid_sources[0x1d]	3317	1			T3	3		T14	2		T16	18
valid_sources[0x1e]	1922	1			T7	4		T32	2		T22	30
valid_sources[0x1f]	2256	1			T3	1		T16	6		T32	2
valid_sources[0x20]	2388	1			T3	7		T4	1		T6	1
valid_sources[0x21]	3131	1			T4	2		T7	2		T32	35
valid_sources[0x22]	1935	1			T3	4		T4	2		T32	12
valid_sources[0x23]	2622	1			T15	1		T22	41		T25	4
valid_sources[0x24]	2404	1			T3	6		T4	1		T7	2
valid_sources[0x25]	2845	1			T4	1		T7	1		T8	18
valid_sources[0x26]	2750	1			T3	3		T7	9		T32	8
valid_sources[0x27]	4567	1			T3	4		T7	3		T32	2
valid_sources[0x28]	2675	1			T7	1		T32	3		T22	47
valid_sources[0x29]	7854	1			T3	1		T6	1		T7	1
valid_sources[0x2a]	2738	1			T3	8		T4	6		T7	2
valid_sources[0x2b]	1889	1			T3	8		T22	39		T25	3
valid_sources[0x2c]	1927	1			T3	4		T32	2		T22	34
valid_sources[0x2d]	2603	1			T3	1		T4	2		T32	12
valid_sources[0x2e]	2121	1			T3	9		T15	1		T22	23
valid_sources[0x2f]	2741	1			T3	4		T32	5		T22	38
valid_sources[0x30]	2444	1			T2	29		T4	3		T15	5
valid_sources[0x31]	2601	1			T3	6		T4	1		T15	1
valid_sources[0x32]	2107	1			T6	1		T15	1		T32	7
valid_sources[0x33]	2067	1			T6	1		T7	1		T32	10
valid_sources[0x34]	4134	1			T3	5		T6	1		T7	3
valid_sources[0x35]	1866	1			T3	2		T6	1		T32	2
valid_sources[0x36]	2489	1			T3	5		T7	1		T32	17
valid_sources[0x37]	2206	1			T3	4		T6	1		T32	42
valid_sources[0x38]	2696	1			T16	18		T32	1		T22	37
valid_sources[0x39]	1836	1			T3	1		T15	1		T32	21
valid_sources[0x3a]	11286	1			T4	2		T32	4		T22	35
valid_sources[0x3b]	2617	1			T3	1		T32	3		T22	42
valid_sources[0x3c]	2266	1			T7	4		T8	25		T15	2
valid_sources[0x3d]	1822	1			T3	1		T32	7		T22	36
valid_sources[0x3e]	1875	1			T3	1		T4	2		T7	1
valid_sources[0x3f]	4106	1			T3	3		T32	4		T22	39
valid_sources[0x40]	2053	1			T3	7		T16	16		T32	4
valid_sources[0x41]	1897	1			T3	4		T7	4		T16	18
valid_sources[0x42]	5322	1			T6	1		T32	10		T22	46
valid_sources[0x43]	2412	1			T3	15		T4	2		T22	37
valid_sources[0x44]	2672	1			T3	1		T7	1		T15	1
valid_sources[0x45]	2239	1			T3	8		T6	1		T15	1
valid_sources[0x46]	4328	1			T3	3		T32	3		T22	21
valid_sources[0x47]	2285	1			T3	1		T6	3		T7	1
valid_sources[0x48]	3328	1			T3	2		T32	8		T22	36
valid_sources[0x49]	2381	1			T3	2		T7	1		T31	33
valid_sources[0x4a]	2491	1			T3	6		T7	1		T32	5
valid_sources[0x4b]	1975	1			T3	1		T7	1		T32	6
valid_sources[0x4c]	1978	1			T2	33		T3	1		T7	1
valid_sources[0x4d]	1937	1			T3	4		T4	2		T6	1
valid_sources[0x4e]	3308	1			T3	8		T32	11		T22	36
valid_sources[0x4f]	1793	1			T3	3		T7	2		T32	7
valid_sources[0x50]	1989	1			T3	11		T7	2		T32	1
valid_sources[0x51]	4730	1			T1	321		T3	8		T4	2
valid_sources[0x52]	1931	1			T3	1		T4	1		T7	5
valid_sources[0x53]	2227	1			T3	7		T4	1		T22	42
valid_sources[0x54]	1972	1			T3	6		T8	6		T32	2
valid_sources[0x55]	1873	1			T7	1		T15	2		T32	4
valid_sources[0x56]	2169	1			T3	1		T32	4		T22	35
valid_sources[0x57]	2838	1			T3	10		T4	1		T6	1
valid_sources[0x58]	2807	1			T3	2		T32	17		T22	27
valid_sources[0x59]	2161	1			T3	1		T22	34		T25	3
valid_sources[0x5a]	2241	1			T3	3		T6	1		T32	7
valid_sources[0x5b]	1714	1			T7	1		T32	7		T22	42
valid_sources[0x5c]	2160	1			T6	1		T7	1		T32	1
valid_sources[0x5d]	1980	1			T3	1		T4	1		T32	16
valid_sources[0x5e]	2221	1			T7	1		T32	10		T22	43
valid_sources[0x5f]	2061	1			T3	2		T4	1		T27	181
valid_sources[0x60]	2075	1			T4	1		T6	1		T15	1
valid_sources[0x61]	1995	1			T3	7		T15	1		T32	15
valid_sources[0x62]	1859	1			T3	3		T22	33		T25	4
valid_sources[0x63]	1682	1			T3	6		T4	1		T15	1
valid_sources[0x64]	1992	1			T3	2		T14	1		T32	4
valid_sources[0x65]	4492	1			T7	1		T22	30		T25	3
valid_sources[0x66]	1982	1			T32	7		T22	36		T25	8
valid_sources[0x67]	3412	1			T7	4		T8	195		T30	1
valid_sources[0x68]	1718	1			T3	1		T15	1		T22	30
valid_sources[0x69]	3321	1			T3	3		T4	1		T32	1
valid_sources[0x6a]	2108	1			T6	1		T15	1		T32	8
valid_sources[0x6b]	2014	1			T3	9		T32	4		T22	37
valid_sources[0x6c]	3317	1			T3	1		T6	1		T15	1
valid_sources[0x6d]	2122	1			T3	2		T6	2		T22	31
valid_sources[0x6e]	1813	1			T3	7		T6	1		T32	3
valid_sources[0x6f]	3496	1			T3	1		T4	1		T6	1
valid_sources[0x70]	1841	1			T3	8		T4	2		T6	1
valid_sources[0x71]	2094	1			T3	19		T4	1		T32	2
valid_sources[0x72]	2880	1			T2	37		T3	11		T16	18
valid_sources[0x73]	1946	1			T3	1		T22	39		T25	10
valid_sources[0x74]	3190	1			T4	1		T16	17		T22	41
valid_sources[0x75]	2855	1			T3	2		T6	1		T22	32
valid_sources[0x76]	1905	1			T22	36		T25	2		T51	1
valid_sources[0x77]	2085	1			T32	6		T22	43		T25	3
valid_sources[0x78]	2589	1			T3	6		T16	16		T22	35
valid_sources[0x79]	1747	1			T6	1		T7	2		T15	3
valid_sources[0x7a]	1888	1			T3	1		T32	1		T22	40
valid_sources[0x7b]	2791	1			T3	4		T4	1		T6	1
valid_sources[0x7c]	2874	1			T3	1		T4	5		T16	13
valid_sources[0x7d]	8020	1			T3	4		T6	1		T7	4
valid_sources[0x7e]	4621	1			T3	5		T4	1		T7	1
valid_sources[0x7f]	1822	1			T3	1		T6	2		T7	4
valid_sources[0x80]	2118	1			T15	2		T32	9		T22	33

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

91237

1

T1

31

T2

12

T3

84

values[0x0]

all_enables

biggest_size

59839

1

T1

25

T2

19

T3

78

values[0x1]

all_enables

biggest_size

32767

1

T1

14

T2

11

T3

44