SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34945 | 1 | T3 | 427 | T25 | 312 | T138 | 293 | ||||
others[1] | 34962 | 1 | T3 | 373 | T6 | 1 | T22 | 1 | ||||
others[2] | 35266 | 1 | T3 | 386 | T25 | 288 | T138 | 312 | ||||
others[3] | 58328 | 1 | T3 | 693 | T22 | 1 | T25 | 515 | ||||
false | 17398 | 1 | T1 | 36 | T3 | 50 | T6 | 2 | ||||
true | 27152 | 1 | T1 | 37 | T2 | 1 | T3 | 101 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35117 | 1 | T3 | 415 | T6 | 1 | T25 | 296 | ||||
others[1] | 35010 | 1 | T3 | 418 | T6 | 1 | T9 | 1 | ||||
others[2] | 35030 | 1 | T3 | 383 | T25 | 285 | T138 | 322 | ||||
others[3] | 58383 | 1 | T3 | 654 | T25 | 508 | T26 | 1 | ||||
false | 11296 | 1 | T1 | 18 | T3 | 50 | T6 | 2 | ||||
true | 21113 | 1 | T1 | 19 | T2 | 1 | T3 | 101 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 657 | 1 | T8 | 7 | T32 | 3 | T22 | 1 | ||||
others[1] | 657 | 1 | T8 | 6 | T9 | 1 | T22 | 6 | ||||
others[2] | 710 | 1 | T8 | 5 | T9 | 1 | T32 | 1 | ||||
others[3] | 1110 | 1 | T6 | 1 | T8 | 10 | T9 | 1 | ||||
false | 13169 | 1 | T1 | 1 | T2 | 1 | T3 | 1 | ||||
true | 3928 | 1 | T6 | 4 | T9 | 2 | T27 | 7 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |