Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T32,T22

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	22995044	5772	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	22995044	240330	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	22995044	9466495	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	22995044	240328	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	22995044	5772	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	22995044	240330	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	22995044	9466495	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	22995044	240328	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22995044	5772	0	0
T1	10672	9	0	0
T2	3647	0	0	0
T3	60066	19	0	0
T4	1295	0	0	0
T5	1923	0	0	0
T6	2822	0	0	0
T7	9676	0	0	0
T8	1868	0	0	0
T9	2947	0	0	0
T10	3117	2	0	0
T22	0	89	0	0
T23	0	43	0	0
T24	0	115	0	0
T25	0	17	0	0
T32	0	11	0	0
T35	0	3	0	0
T74	0	1	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22995044	240330	0	0
T1	10672	344	0	0
T2	3647	0	0	0
T3	60066	736	0	0
T4	1295	0	0	0
T5	1923	0	0	0
T6	2822	0	0	0
T7	9676	0	0	0
T8	1868	0	0	0
T9	2947	0	0	0
T10	3117	255	0	0
T22	0	2019	0	0
T23	0	1016	0	0
T24	0	2202	0	0
T25	0	456	0	0
T32	0	374	0	0
T35	0	432	0	0
T74	0	13	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22995044	9466495	0	0
T1	10672	5623	0	0
T2	3647	1105	0	0
T3	60066	36193	0	0
T4	1295	846	0	0
T5	1923	0	0	0
T6	2822	0	0	0
T7	9676	3750	0	0
T8	1868	0	0	0
T9	2947	0	0	0
T10	3117	1964	0	0
T15	0	254	0	0
T16	0	1154	0	0
T31	0	1320	0	0
T32	0	19737	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22995044	240328	0	0
T1	10672	344	0	0
T2	3647	0	0	0
T3	60066	736	0	0
T4	1295	0	0	0
T5	1923	0	0	0
T6	2822	0	0	0
T7	9676	0	0	0
T8	1868	0	0	0
T9	2947	0	0	0
T10	3117	252	0	0
T22	0	2019	0	0
T23	0	1016	0	0
T24	0	2202	0	0
T25	0	456	0	0
T32	0	368	0	0
T35	0	432	0	0
T74	0	13	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22995044	5772	0	0
T1	10672	9	0	0
T2	3647	0	0	0
T3	60066	19	0	0
T4	1295	0	0	0
T5	1923	0	0	0
T6	2822	0	0	0
T7	9676	0	0	0
T8	1868	0	0	0
T9	2947	0	0	0
T10	3117	2	0	0
T22	0	89	0	0
T23	0	43	0	0
T24	0	115	0	0
T25	0	17	0	0
T32	0	11	0	0
T35	0	3	0	0
T74	0	1	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22995044	240330	0	0
T1	10672	344	0	0
T2	3647	0	0	0
T3	60066	736	0	0
T4	1295	0	0	0
T5	1923	0	0	0
T6	2822	0	0	0
T7	9676	0	0	0
T8	1868	0	0	0
T9	2947	0	0	0
T10	3117	255	0	0
T22	0	2019	0	0
T23	0	1016	0	0
T24	0	2202	0	0
T25	0	456	0	0
T32	0	374	0	0
T35	0	432	0	0
T74	0	13	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22995044	9466495	0	0
T1	10672	5623	0	0
T2	3647	1105	0	0
T3	60066	36193	0	0
T4	1295	846	0	0
T5	1923	0	0	0
T6	2822	0	0	0
T7	9676	3750	0	0
T8	1868	0	0	0
T9	2947	0	0	0
T10	3117	1964	0	0
T15	0	254	0	0
T16	0	1154	0	0
T31	0	1320	0	0
T32	0	19737	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22995044	240328	0	0
T1	10672	344	0	0
T2	3647	0	0	0
T3	60066	736	0	0
T4	1295	0	0	0
T5	1923	0	0	0
T6	2822	0	0	0
T7	9676	0	0	0
T8	1868	0	0	0
T9	2947	0	0	0
T10	3117	252	0	0
T22	0	2019	0	0
T23	0	1016	0	0
T24	0	2202	0	0
T25	0	456	0	0
T32	0	368	0	0
T35	0	432	0	0
T74	0	13	0	0