Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	23611839	14861	0	0
intr_enable_rd_A	23611839	49263	0	0
reset_en_rd_A	23611839	1954	0	0
reset_en_regwen_rd_A	23611839	1804	0	0
wake_info_capture_dis_rd_A	23611839	1811	0	0
wakeup_en_rd_A	23611839	2752	0	0
wakeup_en_regwen_rd_A	23611839	1883	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23611839	14861	0	0
T12	936	0	0	0
T22	203754	2	0	0
T23	0	3	0	0
T24	0	4	0	0
T25	22788	0	0	0
T26	5309	0	0	0
T33	2626	0	0	0
T34	1805	0	0	0
T40	0	7	0	0
T44	0	84	0	0
T51	17112	0	0	0
T74	3476	0	0	0
T75	4309	0	0	0
T86	0	8	0	0
T87	0	7	0	0
T119	0	11	0	0
T120	0	30	0	0
T121	0	11	0	0
T122	4240	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23611839	49263	0	0
T7	9676	53	0	0
T8	1868	0	0	0
T9	2947	0	0	0
T10	3117	0	0	0
T14	39532	0	0	0
T15	1332	0	0	0
T16	1838	0	0	0
T22	0	1457	0	0
T23	0	1334	0	0
T24	0	1794	0	0
T25	0	85	0	0
T26	0	10	0	0
T27	7924	0	0	0
T30	2221	0	0	0
T31	2182	0	0	0
T52	0	51	0	0
T75	0	34	0	0
T123	0	85	0	0
T124	0	28	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23611839	1954	0	0
T13	736	0	0	0
T17	911	0	0	0
T24	291032	7	0	0
T35	2862	0	0	0
T40	0	12	0	0
T46	0	6	0	0
T52	15926	0	0	0
T70	0	8	0	0
T77	0	4	0	0
T86	0	1	0	0
T116	2496	0	0	0
T120	0	6	0	0
T125	0	16	0	0
T126	0	10	0	0
T127	0	6	0	0
T128	2924	0	0	0
T129	3120	0	0	0
T130	3291	0	0	0
T131	6436	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23611839	1804	0	0
T13	736	0	0	0
T17	911	0	0	0
T24	291032	1	0	0
T35	2862	0	0	0
T40	0	7	0	0
T45	0	3	0	0
T46	0	10	0	0
T52	15926	0	0	0
T70	0	6	0	0
T77	0	7	0	0
T78	0	15	0	0
T116	2496	0	0	0
T120	0	8	0	0
T125	0	12	0	0
T126	0	5	0	0
T128	2924	0	0	0
T129	3120	0	0	0
T130	3291	0	0	0
T131	6436	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23611839	1811	0	0
T12	936	0	0	0
T22	203754	3	0	0
T24	0	4	0	0
T25	22788	0	0	0
T26	5309	0	0	0
T33	2626	0	0	0
T34	1805	0	0	0
T40	0	6	0	0
T45	0	6	0	0
T46	0	5	0	0
T51	17112	0	0	0
T70	0	4	0	0
T74	3476	0	0	0
T75	4309	0	0	0
T78	0	2	0	0
T86	0	2	0	0
T120	0	2	0	0
T122	4240	0	0	0
T125	0	13	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23611839	2752	0	0
T12	936	0	0	0
T22	203754	2	0	0
T24	0	9	0	0
T25	22788	0	0	0
T26	5309	0	0	0
T33	2626	0	0	0
T34	1805	0	0	0
T40	0	8	0	0
T45	0	5	0	0
T46	0	6	0	0
T51	17112	0	0	0
T74	3476	0	0	0
T75	4309	0	0	0
T77	0	4	0	0
T78	0	4	0	0
T86	0	2	0	0
T120	0	15	0	0
T122	4240	0	0	0
T125	0	5	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23611839	1883	0	0
T23	163064	2	0	0
T24	291032	2	0	0
T35	2862	0	0	0
T40	0	5	0	0
T46	0	9	0	0
T52	15926	0	0	0
T70	0	9	0	0
T78	0	9	0	0
T116	2496	0	0	0
T120	0	4	0	0
T123	18188	0	0	0
T124	2228	0	0	0
T125	0	10	0	0
T126	0	1	0	0
T127	0	7	0	0
T128	2924	0	0	0
T129	3120	0	0	0
T132	6217	0	0	0