Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	22995044	51009	0	0
IoStatusRise_A	22995044	56848	0	0
MainStatusFall_A	22995044	51009	0	0
MainStatusRise_A	22995044	56848	0	0
UsbStatusFall_A	22995044	35574	0	0
UsbStatusRise_A	22995044	40021	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22995044	51009	0	0
T1	10672	32	0	0
T2	3647	16	0	0
T3	60066	86	0	0
T4	1295	8	0	0
T5	1923	0	0	0
T6	2822	7	0	0
T7	9676	14	0	0
T8	1868	0	0	0
T9	2947	5	0	0
T10	3117	2	0	0
T14	0	60	0	0
T27	0	26	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22995044	56848	0	0
T1	10672	33	0	0
T2	3647	17	0	0
T3	60066	87	0	0
T4	1295	9	0	0
T5	1923	2	0	0
T6	2822	8	0	0
T7	9676	15	0	0
T8	1868	1	0	0
T9	2947	7	0	0
T10	3117	4	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22995044	51009	0	0
T1	10672	32	0	0
T2	3647	16	0	0
T3	60066	86	0	0
T4	1295	8	0	0
T5	1923	0	0	0
T6	2822	7	0	0
T7	9676	14	0	0
T8	1868	0	0	0
T9	2947	5	0	0
T10	3117	2	0	0
T14	0	60	0	0
T27	0	26	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22995044	56848	0	0
T1	10672	33	0	0
T2	3647	17	0	0
T3	60066	87	0	0
T4	1295	9	0	0
T5	1923	2	0	0
T6	2822	8	0	0
T7	9676	15	0	0
T8	1868	1	0	0
T9	2947	7	0	0
T10	3117	4	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22995044	35574	0	0
T1	10672	16	0	0
T2	3647	13	0	0
T3	60066	41	0	0
T4	1295	6	0	0
T5	1923	0	0	0
T6	2822	7	0	0
T7	9676	7	0	0
T8	1868	0	0	0
T9	2947	5	0	0
T10	3117	1	0	0
T14	0	60	0	0
T27	0	26	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22995044	40021	0	0
T1	10672	17	0	0
T2	3647	14	0	0
T3	60066	41	0	0
T4	1295	7	0	0
T5	1923	2	0	0
T6	2822	8	0	0
T7	9676	7	0	0
T8	1868	1	0	0
T9	2947	7	0	0
T10	3117	2	0	0