Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	22995044	56480	0	0
RomAllowCheckGoodState_A	22995044	56531	0	0
RomBlockActiveState_A	22995044	29257	0	0
RomBlockCheckGoodState_A	22995044	414151	0	0
RomIntgChkDisFalse_A	22995044	22317348	0	0
RomIntgChkDisTrue_A	22995044	173727	0	0
RstreqChkEsctimeout_A	22995044	4220	0	0
RstreqChkFsmterm_A	22995044	140	0	0
RstreqChkGlbesc_A	22995044	4221	0	0
RstreqChkMainpd_A	22995044	913384	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22995044	56480	0	0
T1	10672	33	0	0
T2	3647	17	0	0
T3	60066	87	0	0
T4	1295	9	0	0
T5	1923	2	0	0
T6	2822	8	0	0
T7	9676	15	0	0
T8	1868	1	0	0
T9	2947	7	0	0
T10	3117	4	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22995044	56531	0	0
T1	10672	33	0	0
T2	3647	17	0	0
T3	60066	87	0	0
T4	1295	9	0	0
T5	1923	2	0	0
T6	2822	8	0	0
T7	9676	15	0	0
T8	1868	1	0	0
T9	2947	7	0	0
T10	3117	4	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22995044	29257	0	0
T6	2822	650	0	0
T7	9676	0	0	0
T8	1868	0	0	0
T9	2947	492	0	0
T10	3117	0	0	0
T14	39532	0	0	0
T15	1332	0	0	0
T16	1838	0	0	0
T26	0	796	0	0
T27	7924	0	0	0
T30	2221	0	0	0
T80	0	22	0	0
T81	0	764	0	0
T133	0	234	0	0
T134	0	5	0	0
T135	0	1243	0	0
T136	0	8	0	0
T137	0	301	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22995044	414151	0	0
T1	10672	414	0	0
T2	3647	0	0	0
T3	60066	4130	0	0
T4	1295	0	0	0
T5	1923	0	0	0
T6	2822	393	0	0
T7	9676	0	0	0
T8	1868	0	0	0
T9	2947	231	0	0
T10	3117	23	0	0
T22	0	3808	0	0
T25	0	1344	0	0
T26	0	731	0	0
T32	0	412	0	0
T74	0	92	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22995044	22317348	0	0
T1	10672	10621	0	0
T2	3647	3584	0	0
T3	60066	59992	0	0
T4	1295	1236	0	0
T5	1923	1794	0	0
T6	2822	2615	0	0
T7	9676	9587	0	0
T8	1868	1814	0	0
T9	2947	2804	0	0
T10	3117	2947	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22995044	173727	0	0
T6	2822	153	0	0
T7	9676	0	0	0
T8	1868	0	0	0
T9	2947	0	0	0
T10	3117	0	0	0
T14	39532	0	0	0
T15	1332	0	0	0
T16	1838	0	0	0
T25	0	523	0	0
T26	0	2346	0	0
T27	7924	0	0	0
T30	2221	0	0	0
T81	0	53	0	0
T82	0	95	0	0
T133	0	60	0	0
T134	0	102	0	0
T135	0	1955	0	0
T138	0	891	0	0
T139	0	462	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22995044	4220	0	0
T6	2822	3	0	0
T7	9676	0	0	0
T8	1868	0	0	0
T9	2947	1	0	0
T10	3117	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	39532	20	0	0
T15	1332	0	0	0
T16	1838	0	0	0
T22	0	46	0	0
T26	0	2	0	0
T27	7924	6	0	0
T30	2221	0	0	0
T32	0	11	0	0
T33	0	8	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22995044	140	0	0
T11	839	0	0	0
T14	39532	40	0	0
T15	1332	0	0	0
T16	1838	0	0	0
T20	0	20	0	0
T21	0	40	0	0
T22	203754	0	0	0
T25	22788	0	0	0
T27	7924	0	0	0
T28	0	20	0	0
T29	0	20	0	0
T30	2221	0	0	0
T31	2182	0	0	0
T32	43943	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22995044	4221	0	0
T6	2822	3	0	0
T7	9676	0	0	0
T8	1868	0	0	0
T9	2947	1	0	0
T10	3117	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	39532	20	0	0
T15	1332	0	0	0
T16	1838	0	0	0
T22	0	46	0	0
T26	0	2	0	0
T27	7924	6	0	0
T30	2221	0	0	0
T32	0	11	0	0
T33	0	8	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22995044	913384	0	0
T1	10672	1344	0	0
T2	3647	0	0	0
T3	60066	2572	0	0
T4	1295	0	0	0
T5	1923	5	0	0
T6	2822	446	0	0
T7	9676	0	0	0
T8	1868	0	0	0
T9	2947	43	0	0
T10	3117	297	0	0
T22	0	4699	0	0
T27	0	1426	0	0
T30	0	10	0	0
T32	0	1331	0	0