Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	20931104	14463	0	0
intr_enable_rd_A	20931104	32757	0	0
reset_en_rd_A	20931104	1473	0	0
reset_en_regwen_rd_A	20931104	1365	0	0
wake_info_capture_dis_rd_A	20931104	1476	0	0
wakeup_en_rd_A	20931104	2141	0	0
wakeup_en_regwen_rd_A	20931104	1356	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20931104	14463	0	0
T14	623817	30	0	0
T15	116553	7	0	0
T16	2328	0	0	0
T22	0	43	0	0
T40	3265	0	0	0
T44	2557	0	0	0
T45	2741	0	0	0
T50	0	103	0	0
T53	0	1	0	0
T99	3311	0	0	0
T100	15293	0	0	0
T101	6298	0	0	0
T102	3523	0	0	0
T131	0	15	0	0
T132	0	62	0	0
T133	0	18	0	0
T134	0	6	0	0
T135	0	27	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20931104	32757	0	0
T3	36881	110	0	0
T4	4420	12	0	0
T5	2808	0	0	0
T6	62078	120	0	0
T7	2748	0	0	0
T8	864	0	0	0
T9	16711	0	0	0
T10	7551	0	0	0
T14	0	1745	0	0
T16	0	23	0	0
T17	971	0	0	0
T36	2918	0	0	0
T38	0	179	0	0
T56	0	33	0	0
T99	0	49	0	0
T136	0	35	0	0
T137	0	14	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20931104	1473	0	0
T14	623817	10	0	0
T15	116553	0	0	0
T16	2328	0	0	0
T40	3265	0	0	0
T44	2557	0	0	0
T45	2741	0	0	0
T64	0	13	0	0
T65	0	27	0	0
T70	0	21	0	0
T99	3311	0	0	0
T100	15293	0	0	0
T101	6298	0	0	0
T102	3523	0	0	0
T119	0	2	0	0
T131	0	7	0	0
T133	0	5	0	0
T138	0	6	0	0
T139	0	3	0	0
T140	0	14	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20931104	1365	0	0
T14	623817	5	0	0
T15	116553	0	0	0
T16	2328	0	0	0
T40	3265	0	0	0
T44	2557	0	0	0
T45	2741	0	0	0
T64	0	44	0	0
T65	0	22	0	0
T70	0	41	0	0
T72	0	9	0	0
T99	3311	0	0	0
T100	15293	0	0	0
T101	6298	0	0	0
T102	3523	0	0	0
T110	0	10	0	0
T131	0	5	0	0
T138	0	2	0	0
T140	0	6	0	0
T141	0	41	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20931104	1476	0	0
T50	404934	0	0	0
T64	0	27	0	0
T65	0	11	0	0
T70	0	15	0	0
T98	0	3	0	0
T119	0	5	0	0
T131	723899	9	0	0
T132	306679	0	0	0
T133	0	9	0	0
T138	0	10	0	0
T139	0	10	0	0
T140	0	8	0	0
T142	5130	0	0	0
T143	3091	0	0	0
T144	50039	0	0	0
T145	1480	0	0	0
T146	2419	0	0	0
T147	2391	0	0	0
T148	1323	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20931104	2141	0	0
T14	623817	8	0	0
T15	116553	0	0	0
T16	2328	0	0	0
T40	3265	0	0	0
T44	2557	0	0	0
T45	2741	0	0	0
T64	0	8	0	0
T65	0	18	0	0
T70	0	9	0	0
T98	0	4	0	0
T99	3311	0	0	0
T100	15293	0	0	0
T101	6298	0	0	0
T102	3523	0	0	0
T119	0	16	0	0
T131	0	11	0	0
T138	0	9	0	0
T139	0	18	0	0
T140	0	8	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20931104	1356	0	0
T14	623817	15	0	0
T15	116553	0	0	0
T16	2328	0	0	0
T40	3265	0	0	0
T44	2557	0	0	0
T45	2741	0	0	0
T64	0	30	0	0
T65	0	2	0	0
T70	0	19	0	0
T99	3311	0	0	0
T100	15293	0	0	0
T101	6298	0	0	0
T102	3523	0	0	0
T110	0	1	0	0
T131	0	13	0	0
T138	0	8	0	0
T140	0	14	0	0
T141	0	38	0	0
T149	0	2	0	0