Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	20376929	43619	0	0
IoStatusRise_A	20376929	48478	0	0
MainStatusFall_A	20376929	43619	0	0
MainStatusRise_A	20376929	48478	0	0
UsbStatusFall_A	20376929	29559	0	0
UsbStatusRise_A	20376929	33301	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20376929	43619	0	0
T1	1142	2	0	0
T2	6513	6	0	0
T3	36881	88	0	0
T4	4420	10	0	0
T5	2808	0	0	0
T6	62078	84	0	0
T7	2748	6	0	0
T8	864	1	0	0
T9	16711	16	0	0
T10	7551	24	0	0
T36	0	21	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20376929	48478	0	0
T1	1142	3	0	0
T2	6513	7	0	0
T3	36881	90	0	0
T4	4420	12	0	0
T5	2808	4	0	0
T6	62078	86	0	0
T7	2748	8	0	0
T8	864	3	0	0
T9	16711	17	0	0
T10	7551	26	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20376929	43619	0	0
T1	1142	2	0	0
T2	6513	6	0	0
T3	36881	88	0	0
T4	4420	10	0	0
T5	2808	0	0	0
T6	62078	84	0	0
T7	2748	6	0	0
T8	864	1	0	0
T9	16711	16	0	0
T10	7551	24	0	0
T36	0	21	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20376929	48478	0	0
T1	1142	3	0	0
T2	6513	7	0	0
T3	36881	90	0	0
T4	4420	12	0	0
T5	2808	4	0	0
T6	62078	86	0	0
T7	2748	8	0	0
T8	864	3	0	0
T9	16711	17	0	0
T10	7551	26	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20376929	29559	0	0
T1	1142	2	0	0
T2	6513	3	0	0
T3	36881	50	0	0
T4	4420	5	0	0
T5	2808	0	0	0
T6	62078	52	0	0
T7	2748	6	0	0
T8	864	1	0	0
T9	16711	12	0	0
T10	7551	24	0	0
T36	0	6	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20376929	33301	0	0
T1	1142	3	0	0
T2	6513	3	0	0
T3	36881	51	0	0
T4	4420	6	0	0
T5	2808	4	0	0
T6	62078	54	0	0
T7	2748	8	0	0
T8	864	3	0	0
T9	16711	13	0	0
T10	7551	26	0	0