Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	20376929	48080	0	0
RomAllowCheckGoodState_A	20376929	48130	0	0
RomBlockActiveState_A	20376929	27590	0	0
RomBlockCheckGoodState_A	20376929	404777	0	0
RomIntgChkDisFalse_A	20376929	19810419	0	0
RomIntgChkDisTrue_A	20376929	137713	0	0
RstreqChkEsctimeout_A	20376929	3261	0	0
RstreqChkFsmterm_A	20376929	140	0	0
RstreqChkGlbesc_A	20376929	3263	0	0
RstreqChkMainpd_A	20376929	891014	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20376929	48080	0	0
T1	1142	3	0	0
T2	6513	7	0	0
T3	36881	90	0	0
T4	4420	12	0	0
T5	2808	4	0	0
T6	62078	86	0	0
T7	2748	8	0	0
T8	864	3	0	0
T9	16711	17	0	0
T10	7551	26	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20376929	48130	0	0
T1	1142	3	0	0
T2	6513	7	0	0
T3	36881	90	0	0
T4	4420	12	0	0
T5	2808	4	0	0
T6	62078	86	0	0
T7	2748	8	0	0
T8	864	3	0	0
T9	16711	17	0	0
T10	7551	26	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20376929	27590	0	0
T7	2748	447	0	0
T8	864	0	0	0
T9	16711	0	0	0
T10	7551	0	0	0
T11	2469	0	0	0
T13	6924	0	0	0
T17	971	0	0	0
T23	0	300	0	0
T24	0	93	0	0
T36	2918	0	0	0
T37	13442	0	0	0
T38	63231	0	0	0
T150	0	13	0	0
T151	0	16	0	0
T152	0	5	0	0
T153	0	599	0	0
T154	0	1	0	0
T155	0	413	0	0
T156	0	4	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20376929	404777	0	0
T3	36881	2428	0	0
T4	4420	114	0	0
T5	2808	0	0	0
T6	62078	4178	0	0
T7	2748	384	0	0
T8	864	0	0	0
T9	16711	0	0	0
T10	7551	0	0	0
T14	0	3872	0	0
T17	971	0	0	0
T23	0	140	0	0
T36	2918	274	0	0
T37	0	299	0	0
T38	0	4040	0	0
T39	0	2264	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20376929	19810419	0	0
T1	1142	1092	0	0
T2	6513	6415	0	0
T3	36881	36758	0	0
T4	4420	4298	0	0
T5	2808	2535	0	0
T6	62078	61967	0	0
T7	2748	2607	0	0
T8	864	709	0	0
T9	16711	16611	0	0
T10	7551	7403	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20376929	137713	0	0
T14	623817	0	0	0
T15	116553	0	0	0
T16	2328	0	0	0
T18	1377	0	0	0
T23	1897	136	0	0
T24	0	1119	0	0
T40	3265	0	0	0
T43	1194	0	0	0
T44	2557	0	0	0
T45	2741	0	0	0
T95	0	2575	0	0
T99	3311	0	0	0
T144	0	3371	0	0
T151	0	479	0	0
T153	0	136	0	0
T154	0	101	0	0
T157	0	1155	0	0
T158	0	1295	0	0
T159	0	1726	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20376929	3261	0	0
T7	2748	2	0	0
T8	864	1	0	0
T9	16711	0	0	0
T10	7551	7	0	0
T11	2469	1	0	0
T12	0	1	0	0
T13	6924	3	0	0
T17	971	0	0	0
T23	0	4	0	0
T36	2918	0	0	0
T37	13442	0	0	0
T38	63231	0	0	0
T41	0	4	0	0
T42	0	3	0	0
T43	0	2	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20376929	140	0	0
T19	43556	40	0	0
T20	0	20	0	0
T21	0	40	0	0
T25	0	20	0	0
T26	0	20	0	0
T27	1558	0	0	0
T28	5051	0	0	0
T29	5459	0	0	0
T30	1192	0	0	0
T31	1424	0	0	0
T32	3147	0	0	0
T33	3146	0	0	0
T34	3491	0	0	0
T35	15146	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20376929	3263	0	0
T7	2748	2	0	0
T8	864	1	0	0
T9	16711	0	0	0
T10	7551	7	0	0
T11	2469	1	0	0
T12	0	1	0	0
T13	6924	3	0	0
T17	971	0	0	0
T23	0	4	0	0
T36	2918	0	0	0
T37	13442	0	0	0
T38	63231	0	0	0
T41	0	4	0	0
T42	0	3	0	0
T43	0	2	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20376929	891014	0	0
T3	36881	3216	0	0
T4	4420	185	0	0
T5	2808	11	0	0
T6	62078	4987	0	0
T7	2748	399	0	0
T8	864	0	0	0
T9	16711	0	0	0
T10	7551	1109	0	0
T13	0	24	0	0
T17	971	10	0	0
T36	2918	496	0	0
T37	0	329	0	0