Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	536007	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

202978

1

T1

11

T2

57

T3

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	382284	1			T1	35		T2	119		T3	11
values[0x0]	178148	1			T1	12		T2	41		T3	8
values[0x1]	178553	1			T1	10		T2	33		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	424014	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

314971

1

T1

15

T2

86

T3

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2404	1			T2	6		T4	3		T9	28
valid_sources[0x01]	2158	1			T2	2		T9	28		T37	4
valid_sources[0x02]	2362	1			T2	2		T4	1		T9	32
valid_sources[0x03]	3039	1			T2	2		T4	1		T9	30
valid_sources[0x04]	2956	1			T4	1		T9	34		T38	3
valid_sources[0x05]	2066	1			T2	1		T4	1		T9	34
valid_sources[0x06]	2354	1			T4	2		T9	32		T36	3
valid_sources[0x07]	2267	1			T2	1		T9	20		T38	13
valid_sources[0x08]	2168	1			T2	2		T9	26		T10	2
valid_sources[0x09]	2417	1			T4	1		T9	26		T36	6
valid_sources[0x0a]	3799	1			T4	1		T9	24		T38	1
valid_sources[0x0b]	2259	1			T2	1		T9	37		T38	4
valid_sources[0x0c]	2291	1			T2	1		T9	23		T38	5
valid_sources[0x0d]	2782	1			T9	17		T38	6		T24	2
valid_sources[0x0e]	3298	1			T2	1		T3	6		T9	30
valid_sources[0x0f]	3273	1			T2	1		T9	33		T38	6
valid_sources[0x10]	2183	1			T9	23		T38	4		T15	48
valid_sources[0x11]	2532	1			T2	1		T4	1		T9	29
valid_sources[0x12]	2398	1			T2	1		T9	25		T38	6
valid_sources[0x13]	3990	1			T4	1		T9	32		T36	1
valid_sources[0x14]	2314	1			T4	1		T9	19		T38	2
valid_sources[0x15]	3847	1			T4	2		T9	26		T38	2
valid_sources[0x16]	7039	1			T2	4		T9	21		T38	2
valid_sources[0x17]	4538	1			T2	1		T9	28		T36	5
valid_sources[0x18]	3333	1			T9	19		T36	6		T38	1
valid_sources[0x19]	2102	1			T2	1		T4	1		T9	25
valid_sources[0x1a]	5021	1			T2	1		T4	1		T9	26
valid_sources[0x1b]	2327	1			T2	3		T9	23		T54	9
valid_sources[0x1c]	2164	1			T2	1		T9	36		T36	3
valid_sources[0x1d]	2278	1			T9	38		T36	1		T38	4
valid_sources[0x1e]	3181	1			T2	2		T4	1		T9	19
valid_sources[0x1f]	2305	1			T2	2		T9	33		T38	3
valid_sources[0x20]	2186	1			T2	2		T9	31		T38	10
valid_sources[0x21]	2398	1			T2	3		T9	25		T36	1
valid_sources[0x22]	2173	1			T9	29		T36	4		T38	6
valid_sources[0x23]	4488	1			T2	2		T9	23		T36	4
valid_sources[0x24]	2417	1			T2	2		T6	1		T9	28
valid_sources[0x25]	2494	1			T2	1		T9	25		T37	17
valid_sources[0x26]	3084	1			T2	2		T9	32		T36	5
valid_sources[0x27]	2294	1			T9	27		T36	2		T38	3
valid_sources[0x28]	2196	1			T2	1		T4	1		T9	19
valid_sources[0x29]	2706	1			T2	1		T9	28		T44	5
valid_sources[0x2a]	2213	1			T1	1		T2	1		T9	36
valid_sources[0x2b]	2886	1			T2	1		T4	3		T9	38
valid_sources[0x2c]	2294	1			T9	25		T44	4		T38	3
valid_sources[0x2d]	2258	1			T9	37		T36	13		T76	1
valid_sources[0x2e]	2408	1			T4	2		T9	33		T36	5
valid_sources[0x2f]	2338	1			T4	1		T9	29		T38	2
valid_sources[0x30]	3200	1			T9	30		T36	11		T38	5
valid_sources[0x31]	2945	1			T1	3		T2	3		T9	30
valid_sources[0x32]	2760	1			T2	1		T4	1		T9	23
valid_sources[0x33]	4812	1			T9	23		T38	5		T15	57
valid_sources[0x34]	5328	1			T2	1		T9	24		T38	5
valid_sources[0x35]	2849	1			T4	2		T9	22		T37	6
valid_sources[0x36]	2353	1			T2	1		T9	16		T36	2
valid_sources[0x37]	4125	1			T1	1		T9	20		T36	2
valid_sources[0x38]	2445	1			T9	21		T38	4		T24	7
valid_sources[0x39]	3586	1			T9	33		T38	5		T24	3
valid_sources[0x3a]	2160	1			T2	2		T4	1		T9	25
valid_sources[0x3b]	2261	1			T9	19		T36	3		T38	4
valid_sources[0x3c]	3046	1			T1	1		T2	1		T3	1
valid_sources[0x3d]	2154	1			T2	1		T9	25		T38	1
valid_sources[0x3e]	2201	1			T9	24		T36	1		T38	2
valid_sources[0x3f]	2323	1			T2	2		T9	25		T38	1
valid_sources[0x40]	3851	1			T2	1		T9	37		T38	2
valid_sources[0x41]	2555	1			T2	1		T4	1		T9	33
valid_sources[0x42]	2618	1			T9	25		T38	3		T58	3
valid_sources[0x43]	2231	1			T9	31		T38	4		T15	29
valid_sources[0x44]	2188	1			T9	23		T38	3		T76	2
valid_sources[0x45]	2246	1			T4	1		T9	27		T38	2
valid_sources[0x46]	2381	1			T2	1		T4	1		T9	32
valid_sources[0x47]	4317	1			T9	25		T38	4		T39	12
valid_sources[0x48]	3252	1			T2	1		T9	23		T38	1
valid_sources[0x49]	2215	1			T2	1		T9	20		T38	1
valid_sources[0x4a]	3395	1			T4	1		T9	29		T38	3
valid_sources[0x4b]	2173	1			T2	1		T9	26		T38	2
valid_sources[0x4c]	2314	1			T9	25		T38	1		T24	8
valid_sources[0x4d]	2388	1			T9	24		T10	2		T38	1
valid_sources[0x4e]	2222	1			T9	18		T38	4		T58	6
valid_sources[0x4f]	3052	1			T2	1		T9	28		T38	6
valid_sources[0x50]	2353	1			T4	1		T9	26		T38	2
valid_sources[0x51]	2168	1			T9	22		T36	2		T38	6
valid_sources[0x52]	2063	1			T9	31		T36	1		T38	4
valid_sources[0x53]	1936	1			T9	30		T44	5		T36	1
valid_sources[0x54]	3549	1			T2	3		T4	1		T9	33
valid_sources[0x55]	2068	1			T2	1		T9	32		T38	7
valid_sources[0x56]	3293	1			T1	4		T9	34		T36	4
valid_sources[0x57]	2175	1			T9	20		T38	4		T15	42
valid_sources[0x58]	2176	1			T9	38		T36	3		T38	5
valid_sources[0x59]	3453	1			T4	1		T9	22		T36	1
valid_sources[0x5a]	2218	1			T2	1		T4	1		T9	20
valid_sources[0x5b]	2142	1			T2	2		T9	26		T38	2
valid_sources[0x5c]	2991	1			T1	2		T2	1		T3	2
valid_sources[0x5d]	6200	1			T9	37		T36	1		T58	2
valid_sources[0x5e]	4173	1			T9	29		T36	1		T38	5
valid_sources[0x5f]	2385	1			T2	1		T9	22		T36	3
valid_sources[0x60]	2401	1			T1	6		T2	1		T9	30
valid_sources[0x61]	3173	1			T2	3		T9	26		T36	3
valid_sources[0x62]	2461	1			T9	26		T38	5		T39	18
valid_sources[0x63]	2376	1			T2	1		T4	1		T9	28
valid_sources[0x64]	2988	1			T9	21		T36	2		T38	3
valid_sources[0x65]	2362	1			T1	3		T2	2		T9	22
valid_sources[0x66]	2159	1			T2	1		T9	23		T36	1
valid_sources[0x67]	2324	1			T2	2		T3	1		T9	25
valid_sources[0x68]	2296	1			T2	3		T4	1		T9	21
valid_sources[0x69]	2214	1			T4	1		T9	29		T38	4
valid_sources[0x6a]	2078	1			T2	2		T4	2		T9	28
valid_sources[0x6b]	2515	1			T9	22		T38	4		T24	8
valid_sources[0x6c]	2061	1			T2	1		T4	4		T9	26
valid_sources[0x6d]	2822	1			T2	1		T9	23		T38	2
valid_sources[0x6e]	7551	1			T9	28		T38	2		T39	8
valid_sources[0x6f]	2337	1			T9	32		T36	1		T38	1
valid_sources[0x70]	2142	1			T2	1		T9	27		T38	4
valid_sources[0x71]	2357	1			T2	1		T9	27		T38	4
valid_sources[0x72]	2422	1			T9	23		T38	3		T15	52
valid_sources[0x73]	3151	1			T2	2		T9	27		T38	3
valid_sources[0x74]	3178	1			T4	1		T9	20		T36	5
valid_sources[0x75]	2368	1			T2	2		T9	26		T38	1
valid_sources[0x76]	2443	1			T2	1		T9	33		T38	2
valid_sources[0x77]	2248	1			T2	1		T9	32		T36	3
valid_sources[0x78]	2438	1			T2	1		T4	1		T9	27
valid_sources[0x79]	3067	1			T9	29		T38	2		T54	5
valid_sources[0x7a]	2280	1			T2	2		T9	21		T36	2
valid_sources[0x7b]	2668	1			T2	1		T9	32		T36	3
valid_sources[0x7c]	2412	1			T2	1		T7	277		T9	34
valid_sources[0x7d]	2233	1			T4	2		T9	30		T36	5
valid_sources[0x7e]	2072	1			T2	1		T4	1		T9	23
valid_sources[0x7f]	2530	1			T2	1		T4	1		T9	27
valid_sources[0x80]	2147	1			T2	1		T9	34		T38	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

100778

1

T1

7

T2

42

T3

3

values[0x0]

all_enables

biggest_size

66112

1

T1

4

T2

12

T3

4

values[0x1]

all_enables

biggest_size

36088

1

T2

3

T4

5

T5

3