SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35099 | 1 | T9 | 2 | T38 | 391 | T24 | 284 | ||||
others[1] | 35080 | 1 | T38 | 417 | T24 | 306 | T196 | 402 | ||||
others[2] | 34928 | 1 | T10 | 1 | T38 | 422 | T24 | 319 | ||||
others[3] | 58478 | 1 | T9 | 2 | T10 | 2 | T38 | 648 | ||||
false | 19966 | 1 | T1 | 3 | T7 | 30 | T9 | 281 | ||||
true | 30330 | 1 | T1 | 4 | T2 | 1 | T3 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35185 | 1 | T38 | 382 | T24 | 292 | T196 | 398 | ||||
others[1] | 35180 | 1 | T9 | 1 | T38 | 423 | T24 | 304 | ||||
others[2] | 34944 | 1 | T38 | 429 | T24 | 301 | T196 | 407 | ||||
others[3] | 58280 | 1 | T9 | 4 | T38 | 617 | T24 | 512 | ||||
false | 12593 | 1 | T1 | 5 | T7 | 15 | T9 | 143 | ||||
true | 23010 | 1 | T1 | 6 | T2 | 1 | T3 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 706 | 1 | T9 | 12 | T36 | 1 | T37 | 1 | ||||
others[1] | 652 | 1 | T9 | 5 | T37 | 1 | T15 | 5 | ||||
others[2] | 768 | 1 | T9 | 9 | T36 | 1 | T37 | 2 | ||||
others[3] | 1169 | 1 | T4 | 2 | T5 | 2 | T9 | 14 | ||||
false | 14468 | 1 | T1 | 3 | T2 | 1 | T3 | 5 | ||||
true | 4414 | 1 | T1 | 2 | T4 | 7 | T5 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |