Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T44,T38

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	25069322	6415	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	25069322	256706	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	25069322	10342028	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	25069322	256705	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	25069322	6415	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	25069322	256706	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	25069322	10342028	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	25069322	256705	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25069322	6415	0	0
T7	17244	6	0	0
T8	1246	1	0	0
T9	198675	85	0	0
T10	2053	0	0	0
T15	0	58	0	0
T24	0	24	0	0
T36	6850	0	0	0
T37	3473	0	0	0
T38	43263	27	0	0
T39	0	5	0	0
T40	0	18	0	0
T41	2340	0	0	0
T42	1885	0	0	0
T44	1927	2	0	0
T45	0	2	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25069322	256706	0	0
T7	17244	304	0	0
T8	1246	10	0	0
T9	198675	2248	0	0
T10	2053	0	0	0
T15	0	1645	0	0
T24	0	1234	0	0
T36	6850	0	0	0
T37	3473	0	0	0
T38	43263	1432	0	0
T39	0	130	0	0
T40	0	623	0	0
T41	2340	0	0	0
T42	1885	0	0	0
T44	1927	161	0	0
T45	0	383	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25069322	10342028	0	0
T2	9031	5941	0	0
T3	3124	0	0	0
T4	7207	0	0	0
T5	1453	0	0	0
T6	1646	0	0	0
T7	17244	9210	0	0
T8	1246	948	0	0
T9	198675	80814	0	0
T10	2053	0	0	0
T38	0	22198	0	0
T39	0	2690	0	0
T44	1927	213	0	0
T54	0	6384	0	0
T58	0	2589	0	0
T76	0	3128	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25069322	256705	0	0
T7	17244	304	0	0
T8	1246	10	0	0
T9	198675	2253	0	0
T10	2053	0	0	0
T15	0	1645	0	0
T24	0	1234	0	0
T36	6850	0	0	0
T37	3473	0	0	0
T38	43263	1432	0	0
T39	0	130	0	0
T40	0	623	0	0
T41	2340	0	0	0
T42	1885	0	0	0
T44	1927	161	0	0
T45	0	383	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25069322	6415	0	0
T7	17244	6	0	0
T8	1246	1	0	0
T9	198675	85	0	0
T10	2053	0	0	0
T15	0	58	0	0
T24	0	24	0	0
T36	6850	0	0	0
T37	3473	0	0	0
T38	43263	27	0	0
T39	0	5	0	0
T40	0	18	0	0
T41	2340	0	0	0
T42	1885	0	0	0
T44	1927	2	0	0
T45	0	2	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25069322	256706	0	0
T7	17244	304	0	0
T8	1246	10	0	0
T9	198675	2248	0	0
T10	2053	0	0	0
T15	0	1645	0	0
T24	0	1234	0	0
T36	6850	0	0	0
T37	3473	0	0	0
T38	43263	1432	0	0
T39	0	130	0	0
T40	0	623	0	0
T41	2340	0	0	0
T42	1885	0	0	0
T44	1927	161	0	0
T45	0	383	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25069322	10342028	0	0
T2	9031	5941	0	0
T3	3124	0	0	0
T4	7207	0	0	0
T5	1453	0	0	0
T6	1646	0	0	0
T7	17244	9210	0	0
T8	1246	948	0	0
T9	198675	80814	0	0
T10	2053	0	0	0
T38	0	22198	0	0
T39	0	2690	0	0
T44	1927	213	0	0
T54	0	6384	0	0
T58	0	2589	0	0
T76	0	3128	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25069322	256705	0	0
T7	17244	304	0	0
T8	1246	10	0	0
T9	198675	2253	0	0
T10	2053	0	0	0
T15	0	1645	0	0
T24	0	1234	0	0
T36	6850	0	0	0
T37	3473	0	0	0
T38	43263	1432	0	0
T39	0	130	0	0
T40	0	623	0	0
T41	2340	0	0	0
T42	1885	0	0	0
T44	1927	161	0	0
T45	0	383	0	0