Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	25618644	15491	0	0
intr_enable_rd_A	25618644	50905	0	0
reset_en_rd_A	25618644	996	0	0
reset_en_regwen_rd_A	25618644	892	0	0
wake_info_capture_dis_rd_A	25618644	1059	0	0
wakeup_en_rd_A	25618644	1963	0	0
wakeup_en_regwen_rd_A	25618644	902	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25618644	15491	0	0
T9	198675	7	0	0
T10	2053	0	0	0
T11	2344	0	0	0
T12	2401	0	0	0
T15	0	29	0	0
T22	0	10	0	0
T28	0	39	0	0
T36	6850	0	0	0
T37	3473	0	0	0
T38	43263	0	0	0
T41	2340	0	0	0
T42	1885	0	0	0
T44	1927	0	0	0
T50	0	45	0	0
T51	0	33	0	0
T155	0	113	0	0
T156	0	3	0	0
T157	0	36	0	0
T158	0	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25618644	50905	0	0
T1	2131	15	0	0
T2	9031	0	0	0
T3	3124	0	0	0
T4	7207	0	0	0
T5	1453	0	0	0
T6	1646	0	0	0
T7	17244	0	0	0
T8	1246	0	0	0
T9	198675	1037	0	0
T10	2053	11	0	0
T14	0	1	0	0
T54	0	42	0	0
T58	0	51	0	0
T59	0	9	0	0
T65	0	23	0	0
T77	0	12	0	0
T79	0	24	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25618644	996	0	0
T9	198675	2	0	0
T10	2053	0	0	0
T11	2344	0	0	0
T12	2401	0	0	0
T36	6850	0	0	0
T37	3473	0	0	0
T38	43263	0	0	0
T41	2340	0	0	0
T42	1885	0	0	0
T44	1927	0	0	0
T82	0	21	0	0
T84	0	10	0	0
T106	0	1	0	0
T156	0	4	0	0
T159	0	2	0	0
T160	0	6	0	0
T161	0	6	0	0
T162	0	7	0	0
T163	0	5	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25618644	892	0	0
T9	198675	14	0	0
T10	2053	0	0	0
T11	2344	0	0	0
T12	2401	0	0	0
T36	6850	0	0	0
T37	3473	0	0	0
T38	43263	0	0	0
T41	2340	0	0	0
T42	1885	0	0	0
T44	1927	0	0	0
T82	0	10	0	0
T84	0	4	0	0
T106	0	13	0	0
T156	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0
T162	0	2	0	0
T163	0	6	0	0
T164	0	3	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25618644	1059	0	0
T82	0	19	0	0
T106	0	3	0	0
T156	98807	6	0	0
T159	0	2	0	0
T160	0	8	0	0
T161	0	5	0	0
T162	0	5	0	0
T163	0	4	0	0
T164	0	12	0	0
T165	0	3	0	0
T166	762	0	0	0
T167	13811	0	0	0
T168	23859	0	0	0
T169	15116	0	0	0
T170	7974	0	0	0
T171	3436	0	0	0
T172	35561	0	0	0
T173	2281	0	0	0
T174	1797	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25618644	1963	0	0
T9	198675	8	0	0
T10	2053	0	0	0
T11	2344	0	0	0
T12	2401	0	0	0
T36	6850	0	0	0
T37	3473	0	0	0
T38	43263	0	0	0
T41	2340	0	0	0
T42	1885	0	0	0
T44	1927	0	0	0
T82	0	21	0	0
T84	0	2	0	0
T106	0	3	0	0
T156	0	6	0	0
T161	0	3	0	0
T162	0	6	0	0
T163	0	2	0	0
T164	0	12	0	0
T165	0	3	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25618644	902	0	0
T9	198675	6	0	0
T10	2053	0	0	0
T11	2344	0	0	0
T12	2401	0	0	0
T36	6850	0	0	0
T37	3473	0	0	0
T38	43263	0	0	0
T41	2340	0	0	0
T42	1885	0	0	0
T44	1927	0	0	0
T82	0	20	0	0
T84	0	6	0	0
T106	0	5	0	0
T156	0	6	0	0
T159	0	2	0	0
T160	0	6	0	0
T161	0	3	0	0
T162	0	4	0	0
T164	0	8	0	0