Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	75207966	153202	0	0
StatusRise_A	75207966	171050	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75207966	153202	0	0
T1	6393	15	0	0
T2	27093	24	0	0
T3	9372	12	0	0
T4	21621	54	0	0
T5	4359	24	0	0
T6	4938	0	0	0
T7	51732	57	0	0
T8	3738	6	0	0
T9	596025	1678	0	0
T10	6159	15	0	0
T44	0	12	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75207966	171050	0	0
T1	6393	18	0	0
T2	27093	27	0	0
T3	9372	15	0	0
T4	21621	57	0	0
T5	4359	30	0	0
T6	4938	12	0	0
T7	51732	59	0	0
T8	3738	9	0	0
T9	596025	1923	0	0
T10	6159	18	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	25069322	56883	0	0
StatusRise_A	25069322	63337	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25069322	56883	0	0
T1	2131	5	0	0
T2	9031	10	0	0
T3	3124	4	0	0
T4	7207	18	0	0
T5	1453	8	0	0
T6	1646	0	0	0
T7	17244	25	0	0
T8	1246	2	0	0
T9	198675	612	0	0
T10	2053	5	0	0
T44	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25069322	63337	0	0
T1	2131	6	0	0
T2	9031	11	0	0
T3	3124	5	0	0
T4	7207	19	0	0
T5	1453	10	0	0
T6	1646	4	0	0
T7	17244	26	0	0
T8	1246	3	0	0
T9	198675	699	0	0
T10	2053	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	25069322	56883	0	0
StatusRise_A	25069322	63337	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25069322	56883	0	0
T1	2131	5	0	0
T2	9031	10	0	0
T3	3124	4	0	0
T4	7207	18	0	0
T5	1453	8	0	0
T6	1646	0	0	0
T7	17244	25	0	0
T8	1246	2	0	0
T9	198675	612	0	0
T10	2053	5	0	0
T44	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25069322	63337	0	0
T1	2131	6	0	0
T2	9031	11	0	0
T3	3124	5	0	0
T4	7207	19	0	0
T5	1453	10	0	0
T6	1646	4	0	0
T7	17244	26	0	0
T8	1246	3	0	0
T9	198675	699	0	0
T10	2053	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	25069322	39436	0	0
StatusRise_A	25069322	44376	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25069322	39436	0	0
T1	2131	5	0	0
T2	9031	4	0	0
T3	3124	4	0	0
T4	7207	18	0	0
T5	1453	8	0	0
T6	1646	0	0	0
T7	17244	7	0	0
T8	1246	2	0	0
T9	198675	454	0	0
T10	2053	5	0	0
T44	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25069322	44376	0	0
T1	2131	6	0	0
T2	9031	5	0	0
T3	3124	5	0	0
T4	7207	19	0	0
T5	1453	10	0	0
T6	1646	4	0	0
T7	17244	7	0	0
T8	1246	3	0	0
T9	198675	525	0	0
T10	2053	6	0	0