Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	25069915	5115	0	0
EscTimeoutStoppedByClReset_A	25069322	3436724	0	0
EscTimeoutTriggersReset_A	5439743	333	0	0
RomAllowActiveState_A	25069322	62922	0	0
RomAllowCheckGoodState_A	25069322	62973	0	0
RomBlockActiveState_A	25069322	31867	0	0
RomBlockCheckGoodState_A	25069322	426521	0	0
RomIntgChkDisFalse_A	25069322	24354574	0	0
RomIntgChkDisTrue_A	25069322	163675	0	0
RstreqChkEsctimeout_A	25069322	4705	0	0
RstreqChkFsmterm_A	25069322	160	0	0
RstreqChkGlbesc_A	25069322	4705	0	0
RstreqChkMainpd_A	25069322	973205	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25069915	5115	0	0
T12	2402	20	0	0
T13	0	94	0	0
T14	1727	0	0	0
T15	276455	0	0	0
T16	3763	0	0	0
T24	51100	0	0	0
T39	7639	0	0	0
T45	2909	0	0	0
T54	12274	0	0	0
T58	5753	0	0	0
T76	7823	0	0	0
T92	0	251	0	0
T97	0	22	0	0
T110	0	34	0	0
T169	0	58	0	0
T174	0	20	0	0
T175	0	5	0	0
T176	0	263	0	0
T177	0	3	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25069322	3436724	0	0
T1	2131	148	0	0
T2	9031	1056	0	0
T3	3124	46	0	0
T4	7207	460	0	0
T5	1453	206	0	0
T6	1646	35	0	0
T7	17244	3217	0	0
T8	1246	10	0	0
T9	198675	18437	0	0
T10	2053	129	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5439743	333	0	0
T11	197	2	0	0
T12	203	2	0	0
T13	0	2	0	0
T14	143	0	0	0
T15	53658	0	0	0
T16	360	0	0	0
T24	5274	0	0	0
T39	3141	0	0	0
T54	1252	0	0	0
T58	2223	0	0	0
T76	859	0	0	0
T97	0	2	0	0
T110	0	3	0	0
T114	0	3	0	0
T146	0	7	0	0
T175	0	4	0	0
T176	0	3	0	0
T178	0	5	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25069322	62922	0	0
T1	2131	6	0	0
T2	9031	11	0	0
T3	3124	5	0	0
T4	7207	12	0	0
T5	1453	10	0	0
T6	1646	4	0	0
T7	17244	26	0	0
T8	1246	3	0	0
T9	198675	699	0	0
T10	2053	6	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25069322	62973	0	0
T1	2131	6	0	0
T2	9031	11	0	0
T3	3124	5	0	0
T4	7207	13	0	0
T5	1453	10	0	0
T6	1646	4	0	0
T7	17244	26	0	0
T8	1246	3	0	0
T9	198675	699	0	0
T10	2053	6	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25069322	31867	0	0
T1	2131	224	0	0
T2	9031	0	0	0
T3	3124	0	0	0
T4	7207	0	0	0
T5	1453	0	0	0
T6	1646	0	0	0
T7	17244	0	0	0
T8	1246	0	0	0
T9	198675	0	0	0
T10	2053	146	0	0
T46	0	299	0	0
T80	0	18	0	0
T88	0	615	0	0
T111	0	1141	0	0
T149	0	1194	0	0
T179	0	260	0	0
T180	0	4	0	0
T181	0	171	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25069322	426521	0	0
T1	2131	70	0	0
T2	9031	0	0	0
T3	3124	0	0	0
T4	7207	0	0	0
T5	1453	0	0	0
T6	1646	0	0	0
T7	17244	343	0	0
T8	1246	0	0	0
T9	198675	3309	0	0
T10	2053	52	0	0
T15	0	2455	0	0
T24	0	4168	0	0
T38	0	3146	0	0
T39	0	389	0	0
T40	0	734	0	0
T65	0	253	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25069322	24354574	0	0
T1	2131	1972	0	0
T2	9031	8934	0	0
T3	3124	2758	0	0
T4	7207	6282	0	0
T5	1453	1336	0	0
T6	1646	1330	0	0
T7	17244	17166	0	0
T8	1246	1167	0	0
T9	198675	192102	0	0
T10	2053	840	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25069322	163675	0	0
T1	2131	103	0	0
T2	9031	0	0	0
T3	3124	0	0	0
T4	7207	0	0	0
T5	1453	0	0	0
T6	1646	0	0	0
T7	17244	0	0	0
T8	1246	0	0	0
T9	198675	0	0	0
T10	2053	1132	0	0
T24	0	1691	0	0
T46	0	978	0	0
T104	0	2551	0	0
T111	0	282	0	0
T149	0	2228	0	0
T179	0	705	0	0
T182	0	947	0	0
T183	0	11366	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25069322	4705	0	0
T1	2131	3	0	0
T2	9031	0	0	0
T3	3124	0	0	0
T4	7207	3	0	0
T5	1453	6	0	0
T6	1646	3	0	0
T7	17244	0	0	0
T8	1246	0	0	0
T9	198675	84	0	0
T10	2053	2	0	0
T36	0	5	0	0
T37	0	5	0	0
T41	0	5	0	0
T42	0	2	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25069322	160	0	0
T19	45719	40	0	0
T20	0	20	0	0
T21	0	20	0	0
T25	0	40	0	0
T26	0	40	0	0
T27	2345	0	0	0
T28	235639	0	0	0
T29	2078	0	0	0
T30	4596	0	0	0
T31	2704	0	0	0
T32	56835	0	0	0
T33	1934	0	0	0
T34	4861	0	0	0
T35	4951	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25069322	4705	0	0
T1	2131	3	0	0
T2	9031	0	0	0
T3	3124	0	0	0
T4	7207	3	0	0
T5	1453	6	0	0
T6	1646	3	0	0
T7	17244	0	0	0
T8	1246	0	0	0
T9	198675	84	0	0
T10	2053	2	0	0
T36	0	5	0	0
T37	0	5	0	0
T41	0	5	0	0
T42	0	2	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25069322	973205	0	0
T1	2131	93	0	0
T2	9031	0	0	0
T3	3124	0	0	0
T4	7207	376	0	0
T5	1453	113	0	0
T6	1646	0	0	0
T7	17244	1113	0	0
T8	1246	0	0	0
T9	198675	6611	0	0
T10	2053	72	0	0
T16	0	23	0	0
T36	0	187	0	0
T37	0	160	0	0
T38	0	5100	0	0