Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_wakeup_ctrl_cg_wrap::wakeup_ctrl_cg

Group : pwrmgr_env_pkg::pwrmgr_wakeup_ctrl_cg_wrap::wakeup_ctrl_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

6 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
WakeupAonTimer_ctrl_cg	100.00	1	100	1	64	64
WakeupDbgCable_ctrl_cg	100.00	1	100	1	64	64
WakeupPin_ctrl_cg	100.00	1	100	1	64	64
WakeupSensorCtrl_ctrl_cg	100.00	1	100	1	64	64
WakeupSysrst_ctrl_cg	100.00	1	100	1	64	64
WakeupUsb_ctrl_cg	100.00	1	100	1	64	64

---

Group Instance : WakeupAonTimer_ctrl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupAonTimer_ctrl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupAonTimer_ctrl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
capture_cp	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupAonTimer_ctrl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
wakeup_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupDbgCable_ctrl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupDbgCable_ctrl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupDbgCable_ctrl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
capture_cp	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupDbgCable_ctrl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
wakeup_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupPin_ctrl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupPin_ctrl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupPin_ctrl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
capture_cp	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupPin_ctrl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
wakeup_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupSensorCtrl_ctrl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupSensorCtrl_ctrl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupSensorCtrl_ctrl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
capture_cp	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupSensorCtrl_ctrl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
wakeup_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupSysrst_ctrl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupSysrst_ctrl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupSysrst_ctrl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
capture_cp	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupSysrst_ctrl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
wakeup_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupUsb_ctrl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupUsb_ctrl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupUsb_ctrl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
capture_cp	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupUsb_ctrl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
wakeup_cross	8	0	8	100.00	100	1	1	0

Summary for Variable capture_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for capture_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7535

1

T26

7

T60

8

T61

6

auto[1]

19930

1

T5

50

T6

50

T8

1

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12462

1

T5

25

T6

28

T10

22

auto[1]

15003

1

T5

25

T6

22

T8

1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12855

1

T5

23

T6

30

T10

25

auto[1]

14610

1

T5

27

T6

20

T8

1

---

Summary for Cross wakeup_cross

Samples crossed: enable_cp capture_cp wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for wakeup_cross

Bins

enable_cp	capture_cp	wakeup_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1719	1			T26	1		T60	2		T61	1
auto[0]	auto[0]	auto[1]	1817	1			T26	3		T60	2		T61	2
auto[0]	auto[1]	auto[0]	4627	1			T5	12		T6	18		T10	15
auto[0]	auto[1]	auto[1]	4299	1			T5	13		T6	10		T10	7
auto[1]	auto[0]	auto[0]	1666	1			T60	1		T190	2		T65	3
auto[1]	auto[0]	auto[1]	2333	1			T26	3		T60	3		T61	3
auto[1]	auto[1]	auto[0]	4843	1			T5	11		T6	12		T10	10
auto[1]	auto[1]	auto[1]	6161	1			T5	14		T6	10		T8	1

Summary for Variable capture_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for capture_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7535

1

T26

7

T60

8

T61

6

auto[1]

19930

1

T5

50

T6

50

T8

1

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12458

1

T5

14

T6

21

T10

20

auto[1]

15007

1

T5

36

T6

29

T8

1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13138

1

T5

25

T6

25

T8

1

auto[1]

14327

1

T5

25

T6

25

T10

19

---

Summary for Cross wakeup_cross

Samples crossed: enable_cp capture_cp wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for wakeup_cross

Bins

enable_cp	capture_cp	wakeup_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1722	1			T26	2		T60	2		T61	1
auto[0]	auto[0]	auto[1]	1776	1			T26	3		T61	1		T65	3
auto[0]	auto[1]	auto[0]	4787	1			T5	8		T6	10		T10	15
auto[0]	auto[1]	auto[1]	4173	1			T5	6		T6	11		T10	5
auto[1]	auto[0]	auto[0]	1745	1			T60	3		T61	1		T190	1
auto[1]	auto[0]	auto[1]	2292	1			T26	2		T60	3		T61	3
auto[1]	auto[1]	auto[0]	4884	1			T5	17		T6	15		T8	1
auto[1]	auto[1]	auto[1]	6086	1			T5	19		T6	14		T10	14

Summary for Variable capture_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for capture_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7535

1

T26

7

T60

8

T61

6

auto[1]

19930

1

T5

50

T6

50

T8

1

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12485

1

T5

28

T6

17

T10

23

auto[1]

14980

1

T5

22

T6

33

T8

1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12881

1

T5

21

T6

15

T8

1

auto[1]

14584

1

T5

29

T6

35

T10

23

---

Summary for Cross wakeup_cross

Samples crossed: enable_cp capture_cp wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for wakeup_cross

Bins

enable_cp	capture_cp	wakeup_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1753	1			T26	2		T60	2		T61	1
auto[0]	auto[0]	auto[1]	1834	1			T26	3		T60	4		T61	1
auto[0]	auto[1]	auto[0]	4575	1			T5	12		T6	5		T10	15
auto[0]	auto[1]	auto[1]	4323	1			T5	16		T6	12		T10	8
auto[1]	auto[0]	auto[0]	1644	1			T26	1		T61	1		T65	4
auto[1]	auto[0]	auto[1]	2304	1			T26	1		T60	2		T61	3
auto[1]	auto[1]	auto[0]	4909	1			T5	9		T6	10		T8	1
auto[1]	auto[1]	auto[1]	6123	1			T5	13		T6	23		T10	15

Summary for Variable capture_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for capture_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7535

1

T26

7

T60

8

T61

6

auto[1]

19930

1

T5

50

T6

50

T8

1

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12303

1

T5

25

T6

21

T10

25

auto[1]

15162

1

T5

25

T6

29

T8

1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12965

1

T5

24

T6

29

T10

24

auto[1]

14500

1

T5

26

T6

21

T8

1

---

Summary for Cross wakeup_cross

Samples crossed: enable_cp capture_cp wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for wakeup_cross

Bins

enable_cp	capture_cp	wakeup_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1707	1			T26	3		T60	3		T61	2
auto[0]	auto[0]	auto[1]	1650	1			T26	1		T60	2		T61	1
auto[0]	auto[1]	auto[0]	4626	1			T5	12		T6	13		T10	13
auto[0]	auto[1]	auto[1]	4320	1			T5	13		T6	8		T10	12
auto[1]	auto[0]	auto[0]	1740	1			T190	2		T65	1		T16	37
auto[1]	auto[0]	auto[1]	2438	1			T26	3		T60	3		T61	3
auto[1]	auto[1]	auto[0]	4892	1			T5	12		T6	16		T10	11
auto[1]	auto[1]	auto[1]	6092	1			T5	13		T6	13		T8	1

Summary for Variable capture_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for capture_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7535

1

T26

7

T60

8

T61

6

auto[1]

19930

1

T5

50

T6

50

T8

1

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12258

1

T5

28

T6

26

T10

22

auto[1]

15207

1

T5

22

T6

24

T8

1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13125

1

T5

28

T6

23

T8

1

auto[1]

14340

1

T5

22

T6

27

T10

22

---

Summary for Cross wakeup_cross

Samples crossed: enable_cp capture_cp wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for wakeup_cross

Bins

enable_cp	capture_cp	wakeup_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1697	1			T26	2		T61	2		T65	2
auto[0]	auto[0]	auto[1]	1757	1			T26	1		T60	2		T190	1
auto[0]	auto[1]	auto[0]	4625	1			T5	17		T6	13		T10	13
auto[0]	auto[1]	auto[1]	4179	1			T5	11		T6	13		T10	9
auto[1]	auto[0]	auto[0]	1777	1			T26	3		T60	4		T61	1
auto[1]	auto[0]	auto[1]	2304	1			T26	1		T60	2		T61	3
auto[1]	auto[1]	auto[0]	5026	1			T5	11		T6	10		T8	1
auto[1]	auto[1]	auto[1]	6100	1			T5	11		T6	14		T10	13

Summary for Variable capture_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for capture_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7535

1

T26

7

T60

8

T61

6

auto[1]

19930

1

T5

50

T6

50

T8

1

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12230

1

T5

22

T6

25

T10

22

auto[1]

15235

1

T5

28

T6

25

T8

1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13117

1

T5

25

T6

24

T10

24

auto[1]

14348

1

T5

25

T6

26

T8

1

---

Summary for Cross wakeup_cross

Samples crossed: enable_cp capture_cp wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for wakeup_cross

Bins

enable_cp	capture_cp	wakeup_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1775	1			T26	1		T61	1		T190	1
auto[0]	auto[0]	auto[1]	1670	1			T26	2		T60	1		T61	1
auto[0]	auto[1]	auto[0]	4567	1			T5	14		T6	13		T10	11
auto[0]	auto[1]	auto[1]	4218	1			T5	8		T6	12		T10	11
auto[1]	auto[0]	auto[0]	1819	1			T26	3		T60	5		T61	1
auto[1]	auto[0]	auto[1]	2271	1			T26	1		T60	2		T61	3
auto[1]	auto[1]	auto[0]	4956	1			T5	11		T6	11		T10	13
auto[1]	auto[1]	auto[1]	6189	1			T5	17		T6	14		T8	1