Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	519196	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

204238

1

T1

24

T2

8

T3

33

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	387506	1			T1	37		T2	39		T3	182
values[0x0]	167923	1			T1	28		T2	16		T3	29
values[0x1]	168005	1			T1	28		T2	6		T3	33

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	410532	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

312902

1

T1

38

T2

20

T3

85

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2724	1			T3	2		T4	2		T6	1
valid_sources[0x01]	3120	1			T1	1		T3	1		T4	2
valid_sources[0x02]	2486	1			T1	5		T3	1		T4	1
valid_sources[0x03]	2656	1			T1	5		T3	1		T4	1
valid_sources[0x04]	9082	1			T3	2		T4	2		T6	8
valid_sources[0x05]	2741	1			T6	3		T10	1		T24	6
valid_sources[0x06]	2857	1			T3	3		T4	1		T6	2
valid_sources[0x07]	2974	1			T3	1		T6	2		T10	6
valid_sources[0x08]	2923	1			T6	1		T7	1		T10	2
valid_sources[0x09]	2583	1			T4	1		T6	7		T7	1
valid_sources[0x0a]	2621	1			T3	1		T4	1		T10	3
valid_sources[0x0b]	2358	1			T3	2		T4	1		T6	8
valid_sources[0x0c]	2326	1			T3	1		T7	3		T14	1
valid_sources[0x0d]	2803	1			T3	2		T4	1		T10	3
valid_sources[0x0e]	2196	1			T4	1		T10	6		T24	1
valid_sources[0x0f]	2505	1			T1	1		T4	1		T6	1
valid_sources[0x10]	2245	1			T4	2		T6	2		T10	3
valid_sources[0x11]	2216	1			T3	2		T10	13		T15	1
valid_sources[0x12]	2654	1			T3	1		T6	8		T7	2
valid_sources[0x13]	2061	1			T7	3		T8	2		T10	1
valid_sources[0x14]	3923	1			T6	2		T7	7		T10	4
valid_sources[0x15]	2306	1			T3	1		T4	1		T7	3
valid_sources[0x16]	2569	1			T65	1		T16	30		T87	7
valid_sources[0x17]	2449	1			T3	3		T4	1		T6	1
valid_sources[0x18]	3014	1			T3	2		T10	5		T65	3
valid_sources[0x19]	2421	1			T4	1		T6	8		T10	5
valid_sources[0x1a]	2436	1			T3	2		T6	2		T10	7
valid_sources[0x1b]	10384	1			T4	1		T40	2		T65	1
valid_sources[0x1c]	2462	1			T4	4		T6	3		T10	4
valid_sources[0x1d]	2540	1			T6	8		T8	1		T10	2
valid_sources[0x1e]	2343	1			T3	3		T6	5		T7	1
valid_sources[0x1f]	2252	1			T3	1		T4	1		T6	4
valid_sources[0x20]	2069	1			T3	1		T6	1		T7	2
valid_sources[0x21]	2476	1			T3	4		T4	1		T6	1
valid_sources[0x22]	3638	1			T3	1		T4	3		T6	2
valid_sources[0x23]	2170	1			T1	1		T4	1		T6	4
valid_sources[0x24]	2622	1			T6	4		T8	2		T10	4
valid_sources[0x25]	2600	1			T4	1		T6	4		T10	8
valid_sources[0x26]	2443	1			T6	13		T24	7		T65	1
valid_sources[0x27]	2354	1			T3	1		T4	1		T6	4
valid_sources[0x28]	2890	1			T4	1		T6	2		T10	6
valid_sources[0x29]	3241	1			T3	1		T24	1		T14	1
valid_sources[0x2a]	4769	1			T4	2		T7	4		T10	5
valid_sources[0x2b]	2332	1			T3	1		T4	3		T6	7
valid_sources[0x2c]	2661	1			T6	3		T10	2		T24	12
valid_sources[0x2d]	2252	1			T10	1		T24	4		T16	33
valid_sources[0x2e]	3077	1			T6	4		T7	1		T8	1
valid_sources[0x2f]	3186	1			T3	1		T4	1		T6	6
valid_sources[0x30]	2330	1			T3	3		T4	3		T6	3
valid_sources[0x31]	2389	1			T3	1		T6	6		T65	1
valid_sources[0x32]	2754	1			T6	13		T10	3		T65	3
valid_sources[0x33]	2602	1			T3	1		T4	2		T7	3
valid_sources[0x34]	2468	1			T1	1		T3	1		T4	3
valid_sources[0x35]	2212	1			T3	1		T6	11		T8	1
valid_sources[0x36]	3669	1			T6	3		T10	1		T40	2
valid_sources[0x37]	2427	1			T3	1		T6	4		T10	7
valid_sources[0x38]	2449	1			T3	1		T4	1		T7	4
valid_sources[0x39]	2370	1			T4	1		T6	1		T7	5
valid_sources[0x3a]	3557	1			T3	1		T6	9		T7	3
valid_sources[0x3b]	2227	1			T3	1		T10	3		T65	4
valid_sources[0x3c]	2512	1			T1	3		T3	1		T6	7
valid_sources[0x3d]	2514	1			T3	3		T4	1		T6	4
valid_sources[0x3e]	2112	1			T3	1		T4	1		T6	4
valid_sources[0x3f]	2187	1			T10	1		T24	3		T15	1
valid_sources[0x40]	2867	1			T6	2		T8	1		T10	4
valid_sources[0x41]	2377	1			T3	3		T4	1		T6	2
valid_sources[0x42]	2674	1			T3	2		T10	1		T24	1
valid_sources[0x43]	2660	1			T3	1		T10	2		T65	1
valid_sources[0x44]	3254	1			T3	2		T7	5		T10	3
valid_sources[0x45]	3938	1			T3	2		T6	5		T10	9
valid_sources[0x46]	2233	1			T4	2		T6	1		T8	1
valid_sources[0x47]	2770	1			T4	1		T6	1		T10	8
valid_sources[0x48]	3138	1			T3	3		T4	2		T6	2
valid_sources[0x49]	2531	1			T1	2		T3	3		T4	2
valid_sources[0x4a]	2494	1			T3	1		T4	1		T8	1
valid_sources[0x4b]	2348	1			T3	1		T6	13		T10	4
valid_sources[0x4c]	2237	1			T3	2		T6	3		T10	9
valid_sources[0x4d]	3711	1			T4	3		T5	857		T10	5
valid_sources[0x4e]	2416	1			T3	2		T10	4		T65	2
valid_sources[0x4f]	2316	1			T1	1		T4	1		T8	1
valid_sources[0x50]	2702	1			T3	1		T4	5		T6	5
valid_sources[0x51]	3142	1			T3	1		T6	9		T7	1
valid_sources[0x52]	2281	1			T6	12		T8	1		T10	5
valid_sources[0x53]	3311	1			T3	2		T4	1		T6	3
valid_sources[0x54]	3157	1			T6	3		T7	3		T10	1
valid_sources[0x55]	2366	1			T3	1		T4	2		T10	1
valid_sources[0x56]	2338	1			T3	3		T6	3		T7	2
valid_sources[0x57]	3208	1			T1	7		T3	2		T4	3
valid_sources[0x58]	2205	1			T4	1		T6	3		T7	1
valid_sources[0x59]	3057	1			T3	2		T6	4		T7	1
valid_sources[0x5a]	2279	1			T10	5		T60	1		T15	1
valid_sources[0x5b]	3477	1			T4	1		T6	1		T10	2
valid_sources[0x5c]	2357	1			T3	3		T4	4		T10	2
valid_sources[0x5d]	2418	1			T3	1		T4	1		T7	5
valid_sources[0x5e]	2430	1			T4	2		T6	8		T7	5
valid_sources[0x5f]	2436	1			T1	1		T3	1		T4	1
valid_sources[0x60]	4171	1			T3	1		T4	1		T6	6
valid_sources[0x61]	2364	1			T4	1		T10	1		T24	2
valid_sources[0x62]	2289	1			T3	2		T8	1		T10	5
valid_sources[0x63]	2489	1			T6	1		T10	3		T60	1
valid_sources[0x64]	2527	1			T3	1		T4	2		T6	1
valid_sources[0x65]	2395	1			T4	2		T7	6		T10	1
valid_sources[0x66]	2464	1			T3	1		T4	2		T6	3
valid_sources[0x67]	2437	1			T3	2		T4	1		T6	12
valid_sources[0x68]	2381	1			T1	2		T6	1		T10	2
valid_sources[0x69]	2286	1			T3	1		T6	2		T7	1
valid_sources[0x6a]	10320	1			T4	2		T6	3		T7	3
valid_sources[0x6b]	2410	1			T4	2		T6	5		T10	11
valid_sources[0x6c]	2392	1			T3	4		T6	1		T7	1
valid_sources[0x6d]	3743	1			T4	2		T6	4		T24	2
valid_sources[0x6e]	2389	1			T3	1		T4	1		T6	4
valid_sources[0x6f]	2220	1			T4	1		T6	11		T8	2
valid_sources[0x70]	3405	1			T1	3		T4	1		T6	1
valid_sources[0x71]	2370	1			T3	4		T4	1		T7	4
valid_sources[0x72]	2101	1			T1	1		T4	1		T6	1
valid_sources[0x73]	3026	1			T1	1		T6	7		T7	8
valid_sources[0x74]	4094	1			T3	2		T4	3		T6	3
valid_sources[0x75]	3262	1			T6	13		T10	3		T60	4
valid_sources[0x76]	2598	1			T3	1		T6	4		T10	3
valid_sources[0x77]	2318	1			T4	5		T6	1		T10	3
valid_sources[0x78]	3384	1			T6	3		T10	4		T65	2
valid_sources[0x79]	2662	1			T3	1		T10	2		T24	10
valid_sources[0x7a]	2527	1			T4	1		T6	7		T7	5
valid_sources[0x7b]	3305	1			T3	2		T10	1		T24	3
valid_sources[0x7c]	2502	1			T1	2		T3	1		T6	7
valid_sources[0x7d]	2998	1			T4	2		T6	3		T10	7
valid_sources[0x7e]	2387	1			T4	1		T6	10		T7	5
valid_sources[0x7f]	3489	1			T3	1		T4	1		T6	16
valid_sources[0x80]	2564	1			T3	2		T8	1		T10	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

107383

1

T1

9

T2

4

T3

20

values[0x0]

all_enables

biggest_size

62753

1

T1

12

T2

4

T3

9

values[0x1]

all_enables

biggest_size

34102

1

T1

3

T3

4

T4

2