SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35011 | 1 | T2 | 1 | T5 | 402 | T6 | 314 | ||||
others[1] | 35204 | 1 | T5 | 406 | T6 | 297 | T10 | 405 | ||||
others[2] | 34892 | 1 | T5 | 385 | T6 | 283 | T10 | 403 | ||||
others[3] | 58235 | 1 | T5 | 694 | T6 | 504 | T10 | 689 | ||||
false | 18562 | 1 | T2 | 2 | T5 | 50 | T6 | 50 | ||||
true | 28550 | 1 | T1 | 1 | T2 | 4 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34978 | 1 | T5 | 365 | T6 | 293 | T10 | 388 | ||||
others[1] | 35188 | 1 | T5 | 372 | T6 | 302 | T10 | 405 | ||||
others[2] | 34960 | 1 | T5 | 432 | T6 | 308 | T10 | 371 | ||||
others[3] | 58293 | 1 | T2 | 1 | T5 | 694 | T6 | 502 | ||||
false | 11886 | 1 | T2 | 2 | T5 | 50 | T6 | 50 | ||||
true | 21935 | 1 | T1 | 1 | T2 | 4 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 671 | 1 | T3 | 8 | T4 | 6 | T7 | 2 | ||||
others[1] | 738 | 1 | T3 | 10 | T4 | 4 | T7 | 5 | ||||
others[2] | 730 | 1 | T2 | 1 | T3 | 3 | T4 | 6 | ||||
others[3] | 1150 | 1 | T3 | 7 | T4 | 7 | T7 | 8 | ||||
false | 13881 | 1 | T1 | 1 | T2 | 5 | T3 | 3 | ||||
true | 4214 | 1 | T2 | 3 | T4 | 3 | T7 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |