Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T10,T24

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	26052880	6094	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	26052880	272644	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	26052880	10764644	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	26052880	272653	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	26052880	6094	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	26052880	272644	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	26052880	10764644	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	26052880	272653	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26052880	6094	0	0
T5	35100	26	0	0
T6	21546	22	0	0
T7	5145	0	0	0
T8	2330	1	0	0
T9	2384	0	0	0
T10	53427	24	0	0
T14	3310	0	0	0
T16	0	43	0	0
T17	0	17	0	0
T24	24186	17	0	0
T25	0	20	0	0
T40	2699	1	0	0
T87	0	21	0	0
T88	1264	0	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26052880	272644	0	0
T5	35100	936	0	0
T6	21546	574	0	0
T7	5145	0	0	0
T8	2330	12	0	0
T9	2384	0	0	0
T10	53427	1513	0	0
T14	3310	0	0	0
T16	0	1047	0	0
T17	0	1315	0	0
T24	24186	512	0	0
T25	0	1211	0	0
T40	2699	42	0	0
T87	0	750	0	0
T88	1264	0	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26052880	10764644	0	0
T1	1902	221	0	0
T2	1445	0	0	0
T3	2957	0	0	0
T4	7019	0	0	0
T5	35100	18205	0	0
T6	21546	10408	0	0
T7	5145	0	0	0
T8	2330	1479	0	0
T9	2384	0	0	0
T10	53427	25279	0	0
T24	0	10623	0	0
T25	0	23248	0	0
T26	0	4286	0	0
T40	0	403	0	0
T60	0	2725	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26052880	272653	0	0
T5	35100	936	0	0
T6	21546	574	0	0
T7	5145	0	0	0
T8	2330	12	0	0
T9	2384	0	0	0
T10	53427	1513	0	0
T14	3310	0	0	0
T16	0	1047	0	0
T17	0	1315	0	0
T24	24186	512	0	0
T25	0	1211	0	0
T40	2699	42	0	0
T87	0	750	0	0
T88	1264	0	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26052880	6094	0	0
T5	35100	26	0	0
T6	21546	22	0	0
T7	5145	0	0	0
T8	2330	1	0	0
T9	2384	0	0	0
T10	53427	24	0	0
T14	3310	0	0	0
T16	0	43	0	0
T17	0	17	0	0
T24	24186	17	0	0
T25	0	20	0	0
T40	2699	1	0	0
T87	0	21	0	0
T88	1264	0	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26052880	272644	0	0
T5	35100	936	0	0
T6	21546	574	0	0
T7	5145	0	0	0
T8	2330	12	0	0
T9	2384	0	0	0
T10	53427	1513	0	0
T14	3310	0	0	0
T16	0	1047	0	0
T17	0	1315	0	0
T24	24186	512	0	0
T25	0	1211	0	0
T40	2699	42	0	0
T87	0	750	0	0
T88	1264	0	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26052880	10764644	0	0
T1	1902	221	0	0
T2	1445	0	0	0
T3	2957	0	0	0
T4	7019	0	0	0
T5	35100	18205	0	0
T6	21546	10408	0	0
T7	5145	0	0	0
T8	2330	1479	0	0
T9	2384	0	0	0
T10	53427	25279	0	0
T24	0	10623	0	0
T25	0	23248	0	0
T26	0	4286	0	0
T40	0	403	0	0
T60	0	2725	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26052880	272653	0	0
T5	35100	936	0	0
T6	21546	574	0	0
T7	5145	0	0	0
T8	2330	12	0	0
T9	2384	0	0	0
T10	53427	1513	0	0
T14	3310	0	0	0
T16	0	1047	0	0
T17	0	1315	0	0
T24	24186	512	0	0
T25	0	1211	0	0
T40	2699	42	0	0
T87	0	750	0	0
T88	1264	0	0	0