Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	26607971	14932	0	0
intr_enable_rd_A	26607971	30037	0	0
reset_en_rd_A	26607971	1590	0	0
reset_en_regwen_rd_A	26607971	1396	0	0
wake_info_capture_dis_rd_A	26607971	1334	0	0
wakeup_en_rd_A	26607971	2331	0	0
wakeup_en_regwen_rd_A	26607971	1311	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26607971	14932	0	0
T16	207212	2	0	0
T17	96618	0	0	0
T19	3403	0	0	0
T27	0	1	0	0
T28	0	10	0	0
T43	4885	0	0	0
T47	2001	0	0	0
T49	29229	0	0	0
T54	0	6	0	0
T58	0	37	0	0
T78	0	37	0	0
T87	32286	0	0	0
T139	0	5	0	0
T140	0	67	0	0
T141	0	45	0	0
T142	0	4	0	0
T143	58973	0	0	0
T144	60434	0	0	0
T145	21812	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26607971	30037	0	0
T4	7019	75	0	0
T5	35100	0	0	0
T6	21546	0	0	0
T7	5145	104	0	0
T8	2330	0	0	0
T9	2384	0	0	0
T10	53427	0	0	0
T14	3310	0	0	0
T15	0	23	0	0
T24	24186	182	0	0
T26	0	24	0	0
T61	0	22	0	0
T65	0	74	0	0
T66	0	62	0	0
T88	1264	0	0	0
T89	0	68	0	0
T143	0	118	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26607971	1590	0	0
T69	0	20	0	0
T79	0	1	0	0
T81	0	50	0	0
T92	0	2	0	0
T93	0	6	0	0
T119	0	49	0	0
T146	274390	3	0	0
T147	0	3	0	0
T148	0	8	0	0
T149	0	9	0	0
T150	2945	0	0	0
T151	1906	0	0	0
T152	2540	0	0	0
T153	466521	0	0	0
T154	15075	0	0	0
T155	2552	0	0	0
T156	812	0	0	0
T157	16756	0	0	0
T158	11012	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26607971	1396	0	0
T69	0	37	0	0
T79	0	6	0	0
T81	0	40	0	0
T92	0	10	0	0
T93	0	2	0	0
T119	0	52	0	0
T146	274390	5	0	0
T147	0	11	0	0
T148	0	5	0	0
T149	0	12	0	0
T150	2945	0	0	0
T151	1906	0	0	0
T152	2540	0	0	0
T153	466521	0	0	0
T154	15075	0	0	0
T155	2552	0	0	0
T156	812	0	0	0
T157	16756	0	0	0
T158	11012	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26607971	1334	0	0
T69	0	6	0	0
T81	0	46	0	0
T90	0	8	0	0
T92	0	5	0	0
T119	0	49	0	0
T121	0	6	0	0
T146	274390	6	0	0
T148	0	8	0	0
T150	2945	0	0	0
T151	1906	0	0	0
T152	2540	0	0	0
T153	466521	0	0	0
T154	15075	0	0	0
T155	2552	0	0	0
T156	812	0	0	0
T157	16756	0	0	0
T158	11012	0	0	0
T159	0	8	0	0
T160	0	25	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26607971	2331	0	0
T69	0	9	0	0
T79	0	7	0	0
T90	0	3	0	0
T92	0	6	0	0
T93	0	4	0	0
T119	0	48	0	0
T146	274390	5	0	0
T147	0	2	0	0
T148	0	3	0	0
T149	0	2	0	0
T150	2945	0	0	0
T151	1906	0	0	0
T152	2540	0	0	0
T153	466521	0	0	0
T154	15075	0	0	0
T155	2552	0	0	0
T156	812	0	0	0
T157	16756	0	0	0
T158	11012	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26607971	1311	0	0
T69	0	22	0	0
T79	0	7	0	0
T81	0	29	0	0
T92	0	2	0	0
T93	0	8	0	0
T119	0	25	0	0
T146	274390	4	0	0
T148	0	6	0	0
T149	0	6	0	0
T150	2945	0	0	0
T151	1906	0	0	0
T152	2540	0	0	0
T153	466521	0	0	0
T154	15075	0	0	0
T155	2552	0	0	0
T156	812	0	0	0
T157	16756	0	0	0
T158	11012	0	0	0
T159	0	6	0	0