Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	78158640	146722	0	0
StatusRise_A	78158640	163512	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78158640	146722	0	0
T1	5706	20	0	0
T2	4335	15	0	0
T3	8871	0	0	0
T4	21057	9	0	0
T5	105300	231	0	0
T6	64638	220	0	0
T7	15435	6	0	0
T8	6990	6	0	0
T9	7152	12	0	0
T10	160281	219	0	0
T24	0	205	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78158640	163512	0	0
T1	5706	23	0	0
T2	4335	18	0	0
T3	8871	3	0	0
T4	21057	12	0	0
T5	105300	236	0	0
T6	64638	223	0	0
T7	15435	9	0	0
T8	6990	9	0	0
T9	7152	15	0	0
T10	160281	224	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	26052880	54377	0	0
StatusRise_A	26052880	60431	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26052880	54377	0	0
T1	1902	7	0	0
T2	1445	5	0	0
T3	2957	0	0	0
T4	7019	3	0	0
T5	35100	89	0	0
T6	21546	85	0	0
T7	5145	2	0	0
T8	2330	2	0	0
T9	2384	4	0	0
T10	53427	87	0	0
T24	0	84	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26052880	60431	0	0
T1	1902	8	0	0
T2	1445	6	0	0
T3	2957	1	0	0
T4	7019	4	0	0
T5	35100	91	0	0
T6	21546	86	0	0
T7	5145	3	0	0
T8	2330	3	0	0
T9	2384	5	0	0
T10	53427	89	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	26052880	54377	0	0
StatusRise_A	26052880	60441	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26052880	54377	0	0
T1	1902	7	0	0
T2	1445	5	0	0
T3	2957	0	0	0
T4	7019	3	0	0
T5	35100	89	0	0
T6	21546	85	0	0
T7	5145	2	0	0
T8	2330	2	0	0
T9	2384	4	0	0
T10	53427	87	0	0
T24	0	84	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26052880	60441	0	0
T1	1902	8	0	0
T2	1445	6	0	0
T3	2957	1	0	0
T4	7019	4	0	0
T5	35100	91	0	0
T6	21546	86	0	0
T7	5145	3	0	0
T8	2330	3	0	0
T9	2384	5	0	0
T10	53427	89	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	26052880	37968	0	0
StatusRise_A	26052880	42640	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26052880	37968	0	0
T1	1902	6	0	0
T2	1445	5	0	0
T3	2957	0	0	0
T4	7019	3	0	0
T5	35100	53	0	0
T6	21546	50	0	0
T7	5145	2	0	0
T8	2330	2	0	0
T9	2384	4	0	0
T10	53427	45	0	0
T24	0	37	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26052880	42640	0	0
T1	1902	7	0	0
T2	1445	6	0	0
T3	2957	1	0	0
T4	7019	4	0	0
T5	35100	54	0	0
T6	21546	51	0	0
T7	5145	3	0	0
T8	2330	3	0	0
T9	2384	5	0	0
T10	53427	46	0	0