Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	26053468	5823	0	0
EscTimeoutStoppedByClReset_A	26052880	3808476	0	0
EscTimeoutTriggersReset_A	4730312	315	0	0
RomAllowActiveState_A	26052880	60052	0	0
RomAllowCheckGoodState_A	26052880	60102	0	0
RomBlockActiveState_A	26052880	31003	0	0
RomBlockCheckGoodState_A	26052880	418982	0	0
RomIntgChkDisFalse_A	26052880	25383797	0	0
RomIntgChkDisTrue_A	26052880	145439	0	0
RstreqChkEsctimeout_A	26052880	4496	0	0
RstreqChkFsmterm_A	26052880	160	0	0
RstreqChkGlbesc_A	26052880	4496	0	0
RstreqChkMainpd_A	26052880	1077657	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26053468	5823	0	0
T11	872	7	0	0
T12	0	57	0	0
T16	207213	0	0	0
T17	96618	0	0	0
T18	1564	0	0	0
T41	1376	0	0	0
T42	5991	0	0	0
T47	2002	0	0	0
T87	32286	0	0	0
T94	0	122	0	0
T97	0	93	0	0
T100	0	56	0	0
T143	58974	0	0	0
T144	60434	0	0	0
T161	0	157	0	0
T162	0	94	0	0
T163	0	32	0	0
T164	0	20	0	0
T165	0	3	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26052880	3808476	0	0
T1	1902	39	0	0
T2	1445	77	0	0
T3	2957	5	0	0
T4	7019	38	0	0
T5	35100	5932	0	0
T6	21546	3135	0	0
T7	5145	22	0	0
T8	2330	22	0	0
T9	2384	62	0	0
T10	53427	11474	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4730312	315	0	0
T11	256	4	0	0
T12	0	3	0	0
T13	0	4	0	0
T16	75064	0	0	0
T17	9202	0	0	0
T18	307	0	0	0
T41	424	0	0	0
T42	459	0	0	0
T47	605	0	0	0
T87	6418	0	0	0
T94	0	3	0	0
T97	0	3	0	0
T100	0	3	0	0
T143	5741	0	0	0
T144	5892	0	0	0
T161	0	2	0	0
T166	0	5	0	0
T167	0	3	0	0
T168	0	2	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26052880	60052	0	0
T1	1902	8	0	0
T2	1445	6	0	0
T3	2957	1	0	0
T4	7019	4	0	0
T5	35100	91	0	0
T6	21546	86	0	0
T7	5145	3	0	0
T8	2330	3	0	0
T9	2384	5	0	0
T10	53427	89	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26052880	60102	0	0
T1	1902	8	0	0
T2	1445	6	0	0
T3	2957	1	0	0
T4	7019	4	0	0
T5	35100	91	0	0
T6	21546	86	0	0
T7	5145	3	0	0
T8	2330	3	0	0
T9	2384	5	0	0
T10	53427	89	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26052880	31003	0	0
T2	1445	138	0	0
T3	2957	0	0	0
T4	7019	0	0	0
T5	35100	0	0	0
T6	21546	0	0	0
T7	5145	0	0	0
T8	2330	0	0	0
T9	2384	0	0	0
T10	53427	0	0	0
T24	24186	14	0	0
T41	0	90	0	0
T42	0	1241	0	0
T47	0	143	0	0
T105	0	9	0	0
T145	0	4	0	0
T169	0	247	0	0
T170	0	252	0	0
T171	0	1106	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26052880	418982	0	0
T2	1445	13	0	0
T3	2957	0	0	0
T4	7019	0	0	0
T5	35100	2258	0	0
T6	21546	1333	0	0
T7	5145	0	0	0
T8	2330	0	0	0
T9	2384	0	0	0
T10	53427	4114	0	0
T16	0	1813	0	0
T24	24186	1276	0	0
T25	0	3961	0	0
T40	0	92	0	0
T41	0	67	0	0
T42	0	1074	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26052880	25383797	0	0
T1	1902	1851	0	0
T2	1445	1351	0	0
T3	2957	2899	0	0
T4	7019	6921	0	0
T5	35100	34915	0	0
T6	21546	20639	0	0
T7	5145	5073	0	0
T8	2330	2271	0	0
T9	2384	2310	0	0
T10	53427	53246	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26052880	145439	0	0
T2	1445	28	0	0
T3	2957	0	0	0
T4	7019	0	0	0
T5	35100	0	0	0
T6	21546	841	0	0
T7	5145	0	0	0
T8	2330	0	0	0
T9	2384	0	0	0
T10	53427	0	0	0
T24	24186	400	0	0
T25	0	1762	0	0
T41	0	604	0	0
T42	0	195	0	0
T47	0	244	0	0
T87	0	1058	0	0
T105	0	187	0	0
T107	0	461	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26052880	4496	0	0
T2	1445	2	0	0
T3	2957	0	0	0
T4	7019	0	0	0
T5	35100	0	0	0
T6	21546	0	0	0
T7	5145	0	0	0
T8	2330	0	0	0
T9	2384	0	0	0
T10	53427	0	0	0
T11	0	1	0	0
T14	0	7	0	0
T15	0	3	0	0
T16	0	54	0	0
T17	0	40	0	0
T24	24186	0	0	0
T41	0	4	0	0
T42	0	2	0	0
T46	0	5	0	0
T47	0	2	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26052880	160	0	0
T21	24186	40	0	0
T22	0	40	0	0
T23	0	20	0	0
T29	0	40	0	0
T30	0	20	0	0
T31	4555	0	0	0
T32	4990	0	0	0
T33	3008	0	0	0
T34	7406	0	0	0
T35	1528	0	0	0
T36	22231	0	0	0
T37	2281	0	0	0
T38	3135	0	0	0
T39	22765	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26052880	4496	0	0
T2	1445	2	0	0
T3	2957	0	0	0
T4	7019	0	0	0
T5	35100	0	0	0
T6	21546	0	0	0
T7	5145	0	0	0
T8	2330	0	0	0
T9	2384	0	0	0
T10	53427	0	0	0
T11	0	1	0	0
T14	0	7	0	0
T15	0	3	0	0
T16	0	54	0	0
T17	0	40	0	0
T24	24186	0	0	0
T41	0	4	0	0
T42	0	2	0	0
T46	0	5	0	0
T47	0	2	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26052880	1077657	0	0
T2	1445	18	0	0
T3	2957	0	0	0
T4	7019	0	0	0
T5	35100	3196	0	0
T6	21546	2033	0	0
T7	5145	0	0	0
T8	2330	0	0	0
T9	2384	0	0	0
T10	53427	4867	0	0
T14	0	84	0	0
T15	0	429	0	0
T24	24186	1819	0	0
T25	0	5376	0	0
T40	0	123	0	0
T88	0	5	0	0