Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	41112	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31433

1

T1

1

T2

1

T3

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36354	1			T1	1		T2	1		T3	103
values[0x0]	17821	1			T3	30		T7	54		T8	8
values[0x1]	18370	1			T3	33		T7	24		T8	15

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32941	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

39604

1

T1

1

T2

1

T3

54

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	570	1			T8	1		T92	2		T51	2
valid_sources[0x01]	302	1			T7	1		T44	1		T13	1
valid_sources[0x02]	280	1			T22	1		T46	1		T92	3
valid_sources[0x03]	249	1			T7	1		T46	1		T92	1
valid_sources[0x04]	508	1			T12	3		T27	3		T73	214
valid_sources[0x05]	439	1			T14	5		T60	1		T97	2
valid_sources[0x06]	458	1			T7	1		T92	4		T44	1
valid_sources[0x07]	256	1			T7	1		T22	1		T29	1
valid_sources[0x08]	419	1			T92	1		T41	1		T29	1
valid_sources[0x09]	537	1			T22	1		T92	1		T14	2
valid_sources[0x0a]	226	1			T46	1		T92	2		T13	7
valid_sources[0x0b]	251	1			T46	1		T92	1		T43	8
valid_sources[0x0c]	208	1			T92	4		T44	1		T14	7
valid_sources[0x0d]	286	1			T46	1		T92	1		T44	1
valid_sources[0x0e]	350	1			T49	1		T16	12		T37	2
valid_sources[0x0f]	276	1			T92	2		T14	1		T16	6
valid_sources[0x10]	322	1			T7	2		T43	2		T13	2
valid_sources[0x11]	234	1			T7	2		T46	1		T27	1
valid_sources[0x12]	224	1			T42	7		T44	1		T51	1
valid_sources[0x13]	379	1			T7	1		T92	2		T41	1
valid_sources[0x14]	235	1			T22	1		T11	2		T13	2
valid_sources[0x15]	245	1			T92	1		T42	1		T44	1
valid_sources[0x16]	527	1			T22	1		T92	1		T41	1
valid_sources[0x17]	378	1			T22	1		T11	5		T92	1
valid_sources[0x18]	296	1			T92	2		T41	1		T49	2
valid_sources[0x19]	258	1			T7	1		T41	2		T72	1
valid_sources[0x1a]	248	1			T46	2		T51	1		T28	1
valid_sources[0x1b]	244	1			T92	1		T14	4		T16	1
valid_sources[0x1c]	243	1			T22	2		T92	1		T51	1
valid_sources[0x1d]	361	1			T7	1		T29	1		T28	1
valid_sources[0x1e]	305	1			T7	1		T22	1		T46	1
valid_sources[0x1f]	233	1			T22	1		T46	1		T42	1
valid_sources[0x20]	237	1			T7	1		T46	1		T49	1
valid_sources[0x21]	292	1			T22	1		T14	2		T210	2
valid_sources[0x22]	247	1			T7	1		T22	1		T46	1
valid_sources[0x23]	248	1			T14	4		T71	1		T210	2
valid_sources[0x24]	253	1			T7	1		T93	1		T15	2
valid_sources[0x25]	244	1			T7	1		T51	1		T14	2
valid_sources[0x26]	233	1			T10	1		T13	1		T14	2
valid_sources[0x27]	230	1			T92	3		T13	2		T45	1
valid_sources[0x28]	333	1			T7	1		T22	1		T46	1
valid_sources[0x29]	318	1			T92	3		T41	2		T51	1
valid_sources[0x2a]	250	1			T22	1		T41	1		T14	2
valid_sources[0x2b]	237	1			T7	1		T22	1		T71	1
valid_sources[0x2c]	259	1			T22	2		T46	1		T92	1
valid_sources[0x2d]	325	1			T7	1		T8	2		T92	1
valid_sources[0x2e]	224	1			T92	1		T14	2		T16	1
valid_sources[0x2f]	256	1			T29	2		T51	1		T14	1
valid_sources[0x30]	210	1			T14	1		T71	1		T40	4
valid_sources[0x31]	222	1			T46	2		T11	1		T92	2
valid_sources[0x32]	234	1			T8	1		T44	2		T14	1
valid_sources[0x33]	454	1			T51	1		T14	1		T211	2
valid_sources[0x34]	215	1			T46	1		T12	1		T29	1
valid_sources[0x35]	249	1			T92	2		T49	1		T37	1
valid_sources[0x36]	378	1			T46	1		T92	1		T33	1
valid_sources[0x37]	258	1			T7	1		T22	2		T42	5
valid_sources[0x38]	240	1			T92	1		T33	2		T37	1
valid_sources[0x39]	225	1			T22	1		T92	2		T42	3
valid_sources[0x3a]	310	1			T46	3		T13	1		T38	4
valid_sources[0x3b]	199	1			T11	1		T49	1		T134	1
valid_sources[0x3c]	244	1			T46	2		T13	1		T16	9
valid_sources[0x3d]	304	1			T7	1		T46	1		T11	2
valid_sources[0x3e]	406	1			T8	2		T92	3		T29	1
valid_sources[0x3f]	376	1			T92	2		T51	1		T14	1
valid_sources[0x40]	231	1			T92	2		T71	1		T33	3
valid_sources[0x41]	261	1			T46	2		T41	1		T33	3
valid_sources[0x42]	225	1			T46	1		T36	3		T38	5
valid_sources[0x43]	258	1			T22	3		T92	1		T15	1
valid_sources[0x44]	367	1			T49	1		T59	57		T33	2
valid_sources[0x45]	221	1			T22	2		T92	2		T13	1
valid_sources[0x46]	310	1			T7	2		T46	3		T92	1
valid_sources[0x47]	266	1			T7	1		T11	1		T92	6
valid_sources[0x48]	286	1			T8	2		T50	31		T14	5
valid_sources[0x49]	289	1			T46	1		T94	7		T74	1
valid_sources[0x4a]	297	1			T92	2		T44	2		T49	2
valid_sources[0x4b]	339	1			T7	1		T8	1		T22	1
valid_sources[0x4c]	244	1			T92	4		T13	1		T14	2
valid_sources[0x4d]	214	1			T46	1		T13	3		T14	2
valid_sources[0x4e]	270	1			T7	2		T51	2		T49	1
valid_sources[0x4f]	341	1			T5	1		T7	1		T46	1
valid_sources[0x50]	335	1			T8	2		T41	1		T42	1
valid_sources[0x51]	329	1			T17	1		T92	1		T41	1
valid_sources[0x52]	266	1			T92	1		T60	1		T74	1
valid_sources[0x53]	283	1			T46	1		T92	1		T14	2
valid_sources[0x54]	506	1			T12	3		T71	2		T150	1
valid_sources[0x55]	339	1			T22	1		T12	6		T70	1
valid_sources[0x56]	205	1			T92	1		T41	2		T212	1
valid_sources[0x57]	213	1			T13	1		T14	1		T74	1
valid_sources[0x58]	294	1			T7	1		T92	1		T14	2
valid_sources[0x59]	269	1			T22	1		T44	1		T13	1
valid_sources[0x5a]	314	1			T7	1		T92	1		T13	2
valid_sources[0x5b]	219	1			T92	1		T42	1		T51	2
valid_sources[0x5c]	272	1			T22	2		T92	2		T49	1
valid_sources[0x5d]	330	1			T46	2		T92	3		T36	1
valid_sources[0x5e]	243	1			T46	1		T58	1		T96	2
valid_sources[0x5f]	226	1			T22	2		T43	1		T44	3
valid_sources[0x60]	318	1			T22	1		T92	1		T51	1
valid_sources[0x61]	185	1			T7	1		T14	3		T74	2
valid_sources[0x62]	236	1			T22	2		T46	1		T92	1
valid_sources[0x63]	217	1			T92	1		T48	1		T43	2
valid_sources[0x64]	286	1			T22	2		T92	1		T13	5
valid_sources[0x65]	269	1			T41	1		T51	2		T71	1
valid_sources[0x66]	281	1			T46	1		T92	3		T16	7
valid_sources[0x67]	236	1			T92	2		T43	3		T213	1
valid_sources[0x68]	283	1			T7	1		T22	1		T44	2
valid_sources[0x69]	175	1			T7	2		T46	1		T51	1
valid_sources[0x6a]	354	1			T22	1		T92	4		T44	2
valid_sources[0x6b]	314	1			T42	1		T44	2		T49	2
valid_sources[0x6c]	228	1			T8	1		T11	1		T92	2
valid_sources[0x6d]	267	1			T46	1		T92	1		T42	2
valid_sources[0x6e]	305	1			T2	1		T92	1		T44	1
valid_sources[0x6f]	245	1			T7	2		T46	1		T92	1
valid_sources[0x70]	304	1			T45	2		T33	4		T210	1
valid_sources[0x71]	275	1			T46	1		T47	1		T92	1
valid_sources[0x72]	346	1			T7	1		T8	2		T46	2
valid_sources[0x73]	254	1			T49	1		T16	11		T36	1
valid_sources[0x74]	331	1			T22	1		T42	1		T44	1
valid_sources[0x75]	341	1			T7	1		T92	2		T33	4
valid_sources[0x76]	194	1			T46	1		T42	1		T27	1
valid_sources[0x77]	234	1			T92	1		T43	3		T60	1
valid_sources[0x78]	219	1			T92	1		T44	1		T14	2
valid_sources[0x79]	334	1			T7	1		T22	3		T46	1
valid_sources[0x7a]	211	1			T92	5		T14	2		T214	3
valid_sources[0x7b]	206	1			T43	3		T49	1		T14	2
valid_sources[0x7c]	296	1			T7	1		T8	2		T42	1
valid_sources[0x7d]	235	1			T7	1		T92	4		T13	2
valid_sources[0x7e]	185	1			T92	1		T42	1		T44	1
valid_sources[0x7f]	241	1			T46	1		T41	1		T44	1
valid_sources[0x80]	386	1			T7	3		T92	2		T41	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15420

1

T1

1

T2

1

T3

12

values[0x0]

all_enables

biggest_size

9070

1

T3

6

T7

16

T8

3

values[0x1]

all_enables

biggest_size

6943

1

T3

6

T7

3

T8

5