Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2877361	14270	0	0
intr_enable_rd_A	2877361	2869	0	0
reset_en_rd_A	2877361	1651	0	0
reset_en_regwen_rd_A	2877361	1388	0	0
wake_info_capture_dis_rd_A	2877361	1532	0	0
wakeup_en_rd_A	2877361	2583	0	0
wakeup_en_regwen_rd_A	2877361	1436	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2877361	14270	0	0
T23	10361	598	0	0
T24	2060	278	0	0
T25	2885	527	0	0
T61	10361	629	0	0
T62	5139	6	0	0
T63	9167	9	0	0
T64	10750	8	0	0
T77	3681	58	0	0
T87	6117	578	0	0
T99	4659	262	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2877361	2869	0	0
T11	1206	0	0	0
T12	869	0	0	0
T13	0	43	0	0
T16	0	93	0	0
T17	2200	0	0	0
T18	2776	0	0	0
T38	0	44	0	0
T40	0	31	0	0
T41	3012	0	0	0
T46	3579	19	0	0
T47	15169	0	0	0
T48	15247	0	0	0
T60	0	32	0	0
T72	918	0	0	0
T73	0	40	0	0
T92	2247	0	0	0
T100	0	12	0	0
T121	0	15	0	0
T122	0	53	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2877361	1651	0	0
T23	10361	27	0	0
T61	10361	27	0	0
T62	5139	34	0	0
T64	10750	105	0	0
T99	4659	4	0	0
T114	3587	25	0	0
T123	3091	29	0	0
T124	16147	212	0	0
T125	3767	72	0	0
T126	1408	13	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2877361	1388	0	0
T23	10361	18	0	0
T61	10361	7	0	0
T62	5139	13	0	0
T64	10750	72	0	0
T75	9156	5	0	0
T114	3587	44	0	0
T123	3091	18	0	0
T124	16147	243	0	0
T125	3767	36	0	0
T126	1408	8	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2877361	1532	0	0
T23	10361	41	0	0
T61	10361	16	0	0
T62	5139	18	0	0
T64	10750	99	0	0
T75	9156	16	0	0
T99	4659	6	0	0
T114	3587	49	0	0
T123	3091	16	0	0
T124	16147	218	0	0
T125	3767	34	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2877361	2583	0	0
T23	10361	21	0	0
T61	10361	18	0	0
T62	5139	99	0	0
T64	10750	374	0	0
T75	9156	28	0	0
T99	4659	5	0	0
T114	3587	18	0	0
T123	3091	35	0	0
T124	16147	242	0	0
T125	3767	20	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2877361	1436	0	0
T23	10361	25	0	0
T61	10361	10	0	0
T62	5139	19	0	0
T64	10750	59	0	0
T75	9156	20	0	0
T99	4659	7	0	0
T114	3587	12	0	0
T123	3091	11	0	0
T124	16147	199	0	0
T125	3767	54	0	0