Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	6789039	9762	0	0
StatusRise_A	6789039	13252	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6789039	9762	0	0
T1	2712	3	0	0
T2	6780	3	0	0
T3	17682	6	0	0
T4	4818	0	0	0
T5	4503	0	0	0
T6	4053	3	0	0
T7	23622	84	0	0
T8	14466	21	0	0
T9	3948	3	0	0
T10	6555	0	0	0
T22	0	63	0	0
T46	0	3	0	0
T47	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6789039	13252	0	0
T1	2712	9	0	0
T2	6780	9	0	0
T3	17682	9	0	0
T4	4818	15	0	0
T5	4503	15	0	0
T6	4053	9	0	0
T7	23622	90	0	0
T8	14466	24	0	0
T9	3948	9	0	0
T10	6555	12	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2263013	3290	0	0
StatusRise_A	2263013	4466	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2263013	3290	0	0
T1	904	1	0	0
T2	2260	1	0	0
T3	5894	2	0	0
T4	1606	0	0	0
T5	1501	0	0	0
T6	1351	1	0	0
T7	7874	28	0	0
T8	4822	7	0	0
T9	1316	1	0	0
T10	2185	0	0	0
T22	0	21	0	0
T46	0	1	0	0
T47	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2263013	4466	0	0
T1	904	3	0	0
T2	2260	3	0	0
T3	5894	3	0	0
T4	1606	5	0	0
T5	1501	5	0	0
T6	1351	3	0	0
T7	7874	30	0	0
T8	4822	8	0	0
T9	1316	3	0	0
T10	2185	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2263013	3290	0	0
StatusRise_A	2263013	4466	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2263013	3290	0	0
T1	904	1	0	0
T2	2260	1	0	0
T3	5894	2	0	0
T4	1606	0	0	0
T5	1501	0	0	0
T6	1351	1	0	0
T7	7874	28	0	0
T8	4822	7	0	0
T9	1316	1	0	0
T10	2185	0	0	0
T22	0	21	0	0
T46	0	1	0	0
T47	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2263013	4466	0	0
T1	904	3	0	0
T2	2260	3	0	0
T3	5894	3	0	0
T4	1606	5	0	0
T5	1501	5	0	0
T6	1351	3	0	0
T7	7874	30	0	0
T8	4822	8	0	0
T9	1316	3	0	0
T10	2185	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2263013	3182	0	0
StatusRise_A	2263013	4320	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2263013	3182	0	0
T1	904	1	0	0
T2	2260	1	0	0
T3	5894	2	0	0
T4	1606	0	0	0
T5	1501	0	0	0
T6	1351	1	0	0
T7	7874	28	0	0
T8	4822	7	0	0
T9	1316	1	0	0
T10	2185	0	0	0
T22	0	21	0	0
T46	0	1	0	0
T47	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2263013	4320	0	0
T1	904	3	0	0
T2	2260	3	0	0
T3	5894	3	0	0
T4	1606	5	0	0
T5	1501	5	0	0
T6	1351	3	0	0
T7	7874	30	0	0
T8	4822	8	0	0
T9	1316	3	0	0
T10	2185	4	0	0