Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	2263374	4705	0	0
EscTimeoutStoppedByClReset_A	2263013	94650	0	0
EscTimeoutTriggersReset_A	318985	312	0	0
RomAllowActiveState_A	2263013	4112	0	0
RomAllowCheckGoodState_A	2263013	4162	0	0
RomBlockActiveState_A	2263013	24455	0	0
RomBlockCheckGoodState_A	2263013	15889	0	0
RomIntgChkDisFalse_A	2263013	2073980	0	0
RomIntgChkDisTrue_A	2263013	32218	0	0
RstreqChkEsctimeout_A	2263013	1058	0	0
RstreqChkFsmterm_A	2263013	160	0	0
RstreqChkGlbesc_A	2263013	1058	0	0
RstreqChkMainpd_A	2263013	52189	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2263374	4705	0	0
T1	905	3	0	0
T2	2260	30	0	0
T3	5894	0	0	0
T4	1607	0	0	0
T5	1502	0	0	0
T6	1351	0	0	0
T7	7874	0	0	0
T8	4822	0	0	0
T9	1317	0	0	0
T10	2185	0	0	0
T47	0	60	0	0
T48	0	37	0	0
T93	0	39	0	0
T127	0	57	0	0
T128	0	46	0	0
T129	0	186	0	0
T130	0	33	0	0
T131	0	31	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2263013	94650	0	0
T1	904	13	0	0
T2	2260	30	0	0
T3	5894	33	0	0
T4	1606	34	0	0
T5	1501	42	0	0
T6	1351	72	0	0
T7	7874	1191	0	0
T8	4822	248	0	0
T9	1316	56	0	0
T10	2185	79	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318985	312	0	0
T1	251	3	0	0
T2	202	3	0	0
T3	448	0	0	0
T4	551	0	0	0
T5	519	0	0	0
T6	230	3	0	0
T7	586	0	0	0
T8	387	0	0	0
T9	224	4	0	0
T10	248	0	0	0
T47	0	3	0	0
T48	0	2	0	0
T93	0	2	0	0
T127	0	3	0	0
T128	0	3	0	0
T132	0	4	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2263013	4112	0	0
T1	904	3	0	0
T2	2260	3	0	0
T3	5894	3	0	0
T4	1606	5	0	0
T5	1501	5	0	0
T6	1351	3	0	0
T7	7874	30	0	0
T8	4822	8	0	0
T9	1316	3	0	0
T10	2185	4	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2263013	4162	0	0
T1	904	3	0	0
T2	2260	3	0	0
T3	5894	3	0	0
T4	1606	5	0	0
T5	1501	5	0	0
T6	1351	3	0	0
T7	7874	30	0	0
T8	4822	8	0	0
T9	1316	3	0	0
T10	2185	4	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2263013	24455	0	0
T8	4822	1133	0	0
T9	1316	0	0	0
T10	2185	0	0	0
T11	1206	0	0	0
T17	2200	0	0	0
T18	2776	0	0	0
T22	5477	0	0	0
T27	0	845	0	0
T28	0	1194	0	0
T46	3579	0	0	0
T47	15169	0	0	0
T92	2247	0	0	0
T133	0	1353	0	0
T134	0	96	0	0
T135	0	302	0	0
T136	0	97	0	0
T137	0	1395	0	0
T138	0	289	0	0
T139	0	115	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2263013	15889	0	0
T8	4822	965	0	0
T9	1316	0	0	0
T10	2185	0	0	0
T11	1206	0	0	0
T17	2200	0	0	0
T18	2776	0	0	0
T22	5477	0	0	0
T27	0	893	0	0
T28	0	829	0	0
T46	3579	0	0	0
T47	15169	0	0	0
T92	2247	0	0	0
T133	0	822	0	0
T134	0	2	0	0
T135	0	116	0	0
T137	0	831	0	0
T138	0	90	0	0
T139	0	51	0	0
T140	0	29	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2263013	2073980	0	0
T1	904	721	0	0
T2	2260	2116	0	0
T3	5894	5829	0	0
T4	1606	1257	0	0
T5	1501	1115	0	0
T6	1351	1242	0	0
T7	7874	7725	0	0
T8	4822	4366	0	0
T9	1316	1209	0	0
T10	2185	1907	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2263013	32218	0	0
T8	4822	397	0	0
T9	1316	0	0	0
T10	2185	0	0	0
T11	1206	0	0	0
T17	2200	0	0	0
T18	2776	0	0	0
T22	5477	0	0	0
T27	0	175	0	0
T28	0	397	0	0
T46	3579	0	0	0
T47	15169	0	0	0
T92	2247	0	0	0
T133	0	1151	0	0
T134	0	24	0	0
T135	0	924	0	0
T136	0	44	0	0
T137	0	1676	0	0
T138	0	850	0	0
T139	0	979	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2263013	1058	0	0
T1	904	1	0	0
T2	2260	1	0	0
T3	5894	0	0	0
T4	1606	0	0	0
T5	1501	4	0	0
T6	1351	1	0	0
T7	7874	12	0	0
T8	4822	2	0	0
T9	1316	1	0	0
T10	2185	3	0	0
T22	0	8	0	0
T47	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2263013	160	0	0
T19	44564	40	0	0
T20	0	20	0	0
T21	0	20	0	0
T30	0	40	0	0
T31	0	40	0	0
T32	2261	0	0	0
T33	2300	0	0	0
T34	7716	0	0	0
T35	4568	0	0	0
T36	1771	0	0	0
T37	5006	0	0	0
T38	2461	0	0	0
T39	1829	0	0	0
T40	2788	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2263013	1058	0	0
T1	904	1	0	0
T2	2260	1	0	0
T3	5894	0	0	0
T4	1606	0	0	0
T5	1501	4	0	0
T6	1351	1	0	0
T7	7874	12	0	0
T8	4822	2	0	0
T9	1316	1	0	0
T10	2185	3	0	0
T22	0	8	0	0
T47	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2263013	52189	0	0
T4	1606	24	0	0
T5	1501	0	0	0
T6	1351	0	0	0
T7	7874	1271	0	0
T8	4822	936	0	0
T9	1316	0	0	0
T10	2185	0	0	0
T17	2200	22	0	0
T18	0	16	0	0
T22	5477	942	0	0
T41	0	101	0	0
T42	0	83	0	0
T43	0	565	0	0
T46	3579	0	0	0
T72	0	6	0	0