Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	41232	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31833

1

T1

14

T2

1

T3

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37233	1			T1	31		T2	1		T3	5
values[0x0]	17425	1			T1	34		T3	3		T5	34
values[0x1]	18407	1			T1	29		T3	13		T5	29

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32922	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

40143

1

T1

30

T2

1

T3

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	183	1			T5	2		T43	1		T203	1
valid_sources[0x01]	319	1			T14	1		T16	18		T62	1
valid_sources[0x02]	223	1			T8	1		T204	2		T43	3
valid_sources[0x03]	230	1			T14	1		T24	1		T58	1
valid_sources[0x04]	282	1			T14	1		T15	1		T62	2
valid_sources[0x05]	249	1			T3	1		T5	1		T14	2
valid_sources[0x06]	259	1			T15	1		T41	2		T26	2
valid_sources[0x07]	172	1			T5	1		T14	1		T15	1
valid_sources[0x08]	207	1			T15	1		T88	1		T90	12
valid_sources[0x09]	173	1			T7	1		T204	1		T36	2
valid_sources[0x0a]	282	1			T3	1		T5	3		T24	1
valid_sources[0x0b]	353	1			T8	4		T14	1		T15	1
valid_sources[0x0c]	239	1			T5	2		T14	2		T24	1
valid_sources[0x0d]	256	1			T14	1		T24	2		T61	4
valid_sources[0x0e]	233	1			T5	1		T29	3		T41	1
valid_sources[0x0f]	283	1			T2	1		T41	2		T62	1
valid_sources[0x10]	346	1			T10	1		T14	1		T24	1
valid_sources[0x11]	267	1			T36	1		T39	1		T96	1
valid_sources[0x12]	332	1			T5	1		T10	1		T43	7
valid_sources[0x13]	260	1			T14	2		T24	1		T205	11
valid_sources[0x14]	213	1			T88	2		T44	15		T17	2
valid_sources[0x15]	357	1			T14	1		T24	3		T62	1
valid_sources[0x16]	177	1			T3	2		T14	3		T24	1
valid_sources[0x17]	227	1			T3	1		T14	1		T24	1
valid_sources[0x18]	255	1			T14	1		T15	2		T204	2
valid_sources[0x19]	182	1			T5	1		T36	1		T95	1
valid_sources[0x1a]	267	1			T8	1		T15	3		T13	1
valid_sources[0x1b]	297	1			T5	1		T14	2		T43	8
valid_sources[0x1c]	223	1			T43	2		T37	1		T39	2
valid_sources[0x1d]	207	1			T5	1		T14	3		T62	2
valid_sources[0x1e]	392	1			T1	94		T14	1		T24	1
valid_sources[0x1f]	258	1			T10	1		T43	4		T205	16
valid_sources[0x20]	234	1			T14	2		T15	3		T24	3
valid_sources[0x21]	341	1			T14	1		T11	1		T62	1
valid_sources[0x22]	229	1			T14	1		T36	1		T96	1
valid_sources[0x23]	255	1			T5	1		T204	1		T36	2
valid_sources[0x24]	552	1			T5	1		T41	1		T204	1
valid_sources[0x25]	291	1			T14	2		T15	1		T204	2
valid_sources[0x26]	334	1			T15	1		T24	1		T203	1
valid_sources[0x27]	279	1			T3	1		T8	1		T204	1
valid_sources[0x28]	208	1			T14	1		T15	2		T61	1
valid_sources[0x29]	197	1			T3	1		T41	1		T204	1
valid_sources[0x2a]	375	1			T3	1		T5	1		T14	1
valid_sources[0x2b]	632	1			T10	1		T14	1		T41	5
valid_sources[0x2c]	399	1			T24	1		T27	1		T204	2
valid_sources[0x2d]	259	1			T14	1		T15	1		T41	2
valid_sources[0x2e]	190	1			T5	3		T15	1		T204	1
valid_sources[0x2f]	255	1			T8	1		T41	2		T43	1
valid_sources[0x30]	262	1			T10	1		T36	2		T37	1
valid_sources[0x31]	214	1			T5	1		T41	2		T62	2
valid_sources[0x32]	501	1			T14	1		T204	1		T90	2
valid_sources[0x33]	210	1			T14	1		T41	1		T58	3
valid_sources[0x34]	194	1			T10	2		T15	1		T26	1
valid_sources[0x35]	286	1			T5	1		T14	1		T15	1
valid_sources[0x36]	249	1			T5	2		T88	1		T90	1
valid_sources[0x37]	557	1			T5	1		T24	2		T90	1
valid_sources[0x38]	334	1			T5	1		T61	1		T206	1
valid_sources[0x39]	196	1			T5	1		T87	10		T88	1
valid_sources[0x3a]	229	1			T5	1		T24	1		T204	2
valid_sources[0x3b]	368	1			T5	1		T24	1		T88	1
valid_sources[0x3c]	185	1			T5	1		T8	1		T14	2
valid_sources[0x3d]	424	1			T87	36		T36	2		T200	1
valid_sources[0x3e]	236	1			T5	1		T36	2		T96	7
valid_sources[0x3f]	233	1			T24	2		T43	3		T45	1
valid_sources[0x40]	353	1			T14	1		T16	17		T61	2
valid_sources[0x41]	228	1			T204	1		T33	1		T39	1
valid_sources[0x42]	368	1			T5	1		T15	1		T27	4
valid_sources[0x43]	207	1			T10	1		T204	1		T36	1
valid_sources[0x44]	172	1			T5	1		T14	1		T24	1
valid_sources[0x45]	271	1			T14	1		T62	1		T90	2
valid_sources[0x46]	227	1			T5	1		T14	1		T24	2
valid_sources[0x47]	354	1			T5	2		T15	1		T41	1
valid_sources[0x48]	288	1			T14	1		T90	1		T43	5
valid_sources[0x49]	226	1			T14	1		T28	1		T43	2
valid_sources[0x4a]	199	1			T14	1		T15	1		T61	1
valid_sources[0x4b]	292	1			T24	1		T58	1		T62	1
valid_sources[0x4c]	210	1			T5	2		T24	1		T43	3
valid_sources[0x4d]	352	1			T14	1		T24	1		T204	1
valid_sources[0x4e]	295	1			T5	1		T15	2		T24	1
valid_sources[0x4f]	406	1			T5	1		T43	3		T17	22
valid_sources[0x50]	395	1			T15	2		T43	1		T47	1
valid_sources[0x51]	313	1			T10	2		T41	1		T36	2
valid_sources[0x52]	274	1			T24	1		T41	1		T204	1
valid_sources[0x53]	312	1			T5	1		T39	1		T40	2
valid_sources[0x54]	244	1			T5	2		T14	1		T15	1
valid_sources[0x55]	363	1			T14	2		T27	3		T204	1
valid_sources[0x56]	279	1			T24	1		T90	2		T43	8
valid_sources[0x57]	472	1			T24	1		T61	1		T26	1
valid_sources[0x58]	276	1			T5	2		T14	1		T24	1
valid_sources[0x59]	384	1			T5	1		T44	3		T36	3
valid_sources[0x5a]	206	1			T41	2		T88	1		T91	2
valid_sources[0x5b]	310	1			T14	2		T24	1		T43	1
valid_sources[0x5c]	233	1			T61	2		T28	4		T204	1
valid_sources[0x5d]	263	1			T5	2		T10	1		T41	1
valid_sources[0x5e]	229	1			T17	12		T36	2		T38	5
valid_sources[0x5f]	216	1			T14	3		T204	2		T26	2
valid_sources[0x60]	193	1			T5	1		T24	1		T204	1
valid_sources[0x61]	312	1			T5	1		T14	1		T39	3
valid_sources[0x62]	238	1			T15	3		T24	1		T16	12
valid_sources[0x63]	250	1			T14	1		T24	2		T28	1
valid_sources[0x64]	221	1			T5	2		T24	1		T41	1
valid_sources[0x65]	223	1			T14	3		T41	1		T88	1
valid_sources[0x66]	229	1			T5	2		T14	2		T24	1
valid_sources[0x67]	211	1			T15	1		T41	1		T33	1
valid_sources[0x68]	184	1			T14	1		T90	1		T36	2
valid_sources[0x69]	433	1			T204	1		T43	1		T47	1
valid_sources[0x6a]	418	1			T8	1		T15	1		T41	2
valid_sources[0x6b]	540	1			T14	1		T49	1		T41	1
valid_sources[0x6c]	272	1			T14	1		T41	1		T43	4
valid_sources[0x6d]	264	1			T5	1		T29	1		T204	1
valid_sources[0x6e]	231	1			T5	1		T14	1		T28	2
valid_sources[0x6f]	668	1			T5	2		T36	1		T39	2
valid_sources[0x70]	214	1			T14	2		T36	1		T95	1
valid_sources[0x71]	265	1			T9	1		T15	1		T24	1
valid_sources[0x72]	395	1			T5	1		T14	1		T15	1
valid_sources[0x73]	479	1			T5	3		T14	2		T15	2
valid_sources[0x74]	250	1			T204	1		T36	1		T127	1
valid_sources[0x75]	398	1			T5	2		T61	1		T204	1
valid_sources[0x76]	232	1			T5	2		T14	1		T41	1
valid_sources[0x77]	419	1			T5	1		T15	1		T27	7
valid_sources[0x78]	190	1			T61	1		T58	3		T28	1
valid_sources[0x79]	213	1			T41	1		T90	2		T43	4
valid_sources[0x7a]	258	1			T3	1		T5	2		T10	1
valid_sources[0x7b]	318	1			T5	2		T14	2		T15	1
valid_sources[0x7c]	259	1			T5	3		T15	2		T16	6
valid_sources[0x7d]	283	1			T5	2		T28	2		T43	3
valid_sources[0x7e]	281	1			T5	1		T14	1		T62	1
valid_sources[0x7f]	241	1			T5	1		T14	4		T47	1
valid_sources[0x80]	297	1			T5	1		T24	1		T204	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15841

1

T1

3

T2

1

T3

4

values[0x0]

all_enables

biggest_size

9052

1

T1

6

T3

2

T5

8

values[0x1]

all_enables

biggest_size

6940

1

T1

5

T3

1

T5

5