SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 4 | 1 | T27 | 1 | T139 | 1 | T155 | 1 | ||||
others[1] | 13 | 1 | T47 | 2 | T141 | 1 | T149 | 1 | ||||
others[2] | 15 | 1 | T28 | 1 | T46 | 1 | T38 | 1 | ||||
others[3] | 17 | 1 | T10 | 1 | T27 | 1 | T139 | 2 | ||||
false | 132 | 1 | T10 | 3 | T27 | 1 | T28 | 2 | ||||
true | 2689 | 1 | T1 | 1 | T2 | 3 | T3 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 12 | 1 | T27 | 1 | T46 | 1 | T140 | 1 | ||||
others[1] | 13 | 1 | T28 | 1 | T139 | 1 | T140 | 1 | ||||
others[2] | 7 | 1 | T42 | 1 | T164 | 1 | T165 | 1 | ||||
others[3] | 23 | 1 | T10 | 1 | T28 | 1 | T46 | 1 | ||||
false | 155 | 1 | T10 | 4 | T27 | 3 | T28 | 1 | ||||
true | 2783 | 1 | T1 | 1 | T2 | 3 | T3 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 364 | 1 | T1 | 5 | T5 | 4 | T27 | 1 | ||||
others[1] | 329 | 1 | T1 | 4 | T5 | 2 | T41 | 2 | ||||
others[2] | 328 | 1 | T1 | 5 | T5 | 5 | T10 | 1 | ||||
others[3] | 569 | 1 | T1 | 11 | T5 | 14 | T41 | 1 | ||||
false | 3894 | 1 | T1 | 5 | T2 | 3 | T3 | 5 | ||||
true | 866 | 1 | T1 | 2 | T5 | 1 | T10 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |