Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2892134	13765	0	0
intr_enable_rd_A	2892134	3100	0	0
reset_en_rd_A	2892134	1478	0	0
reset_en_regwen_rd_A	2892134	1357	0	0
wake_info_capture_dis_rd_A	2892134	1330	0	0
wakeup_en_rd_A	2892134	1684	0	0
wakeup_en_regwen_rd_A	2892134	1284	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2892134	13765	0	0
T21	1341	22	0	0
T22	1825	40	0	0
T23	6546	8	0	0
T63	8709	723	0	0
T64	15376	13	0	0
T65	7617	6	0	0
T66	4599	310	0	0
T67	12702	1311	0	0
T74	3290	113	0	0
T79	1513	22	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2892134	3100	0	0
T8	2457	6	0	0
T9	1446	0	0	0
T10	1521	0	0	0
T11	2444	0	0	0
T12	14909	0	0	0
T13	15304	0	0	0
T14	3127	0	0	0
T15	2614	0	0	0
T24	6720	0	0	0
T26	0	15	0	0
T33	0	2	0	0
T34	0	4	0	0
T36	0	62	0	0
T48	1270	0	0	0
T94	0	52	0	0
T127	0	2	0	0
T128	0	74	0	0
T129	0	1	0	0
T130	0	115	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2892134	1478	0	0
T21	1341	10	0	0
T64	15376	125	0	0
T66	4599	9	0	0
T71	3556	41	0	0
T79	1513	5	0	0
T82	5822	1	0	0
T116	30397	426	0	0
T123	3037	43	0	0
T131	3587	34	0	0
T132	26904	304	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2892134	1357	0	0
T64	15376	92	0	0
T71	3556	74	0	0
T72	4021	9	0	0
T79	1513	5	0	0
T82	5822	26	0	0
T116	30397	435	0	0
T123	3037	56	0	0
T131	3587	21	0	0
T132	26904	286	0	0
T133	1530	1	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2892134	1330	0	0
T21	1341	6	0	0
T64	15376	82	0	0
T71	3556	55	0	0
T79	1513	8	0	0
T82	5822	21	0	0
T116	30397	463	0	0
T123	3037	28	0	0
T131	3587	27	0	0
T132	26904	255	0	0
T133	1530	4	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2892134	1684	0	0
T21	1341	11	0	0
T64	15376	269	0	0
T66	4599	17	0	0
T71	3556	21	0	0
T72	4021	9	0	0
T79	1513	9	0	0
T82	5822	21	0	0
T116	30397	440	0	0
T123	3037	8	0	0
T131	3587	26	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2892134	1284	0	0
T21	1341	8	0	0
T64	15376	98	0	0
T66	4599	8	0	0
T71	3556	33	0	0
T72	4021	7	0	0
T79	1513	8	0	0
T82	5822	15	0	0
T116	30397	473	0	0
T123	3037	13	0	0
T131	3587	26	0	0