Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	6885675	9849	0	0
StatusRise_A	6885675	13272	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6885675	9849	0	0
T1	5508	6	0	0
T2	4134	0	0	0
T3	4506	12	0	0
T4	3063	0	0	0
T5	9567	3	0	0
T6	3135	0	0	0
T7	5154	0	0	0
T8	7371	6	0	0
T9	4338	0	0	0
T10	4563	15	0	0
T11	0	3	0	0
T12	0	3	0	0
T14	0	28	0	0
T15	0	8	0	0
T24	0	63	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6885675	13272	0	0
T1	5508	9	0	0
T2	4134	9	0	0
T3	4506	15	0	0
T4	3063	12	0	0
T5	9567	6	0	0
T6	3135	9	0	0
T7	5154	6	0	0
T8	7371	9	0	0
T9	4338	21	0	0
T10	4563	21	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2295225	3324	0	0
StatusRise_A	2295225	4475	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2295225	3324	0	0
T1	1836	2	0	0
T2	1378	0	0	0
T3	1502	4	0	0
T4	1021	0	0	0
T5	3189	1	0	0
T6	1045	0	0	0
T7	1718	0	0	0
T8	2457	2	0	0
T9	1446	0	0	0
T10	1521	5	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	0	10	0	0
T15	0	3	0	0
T24	0	21	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2295225	4475	0	0
T1	1836	3	0	0
T2	1378	3	0	0
T3	1502	5	0	0
T4	1021	4	0	0
T5	3189	2	0	0
T6	1045	3	0	0
T7	1718	2	0	0
T8	2457	3	0	0
T9	1446	7	0	0
T10	1521	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2295225	3324	0	0
StatusRise_A	2295225	4475	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2295225	3324	0	0
T1	1836	2	0	0
T2	1378	0	0	0
T3	1502	4	0	0
T4	1021	0	0	0
T5	3189	1	0	0
T6	1045	0	0	0
T7	1718	0	0	0
T8	2457	2	0	0
T9	1446	0	0	0
T10	1521	5	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	0	10	0	0
T15	0	3	0	0
T24	0	21	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2295225	4475	0	0
T1	1836	3	0	0
T2	1378	3	0	0
T3	1502	5	0	0
T4	1021	4	0	0
T5	3189	2	0	0
T6	1045	3	0	0
T7	1718	2	0	0
T8	2457	3	0	0
T9	1446	7	0	0
T10	1521	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2295225	3201	0	0
StatusRise_A	2295225	4322	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2295225	3201	0	0
T1	1836	2	0	0
T2	1378	0	0	0
T3	1502	4	0	0
T4	1021	0	0	0
T5	3189	1	0	0
T6	1045	0	0	0
T7	1718	0	0	0
T8	2457	2	0	0
T9	1446	0	0	0
T10	1521	5	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	0	8	0	0
T15	0	2	0	0
T24	0	21	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2295225	4322	0	0
T1	1836	3	0	0
T2	1378	3	0	0
T3	1502	5	0	0
T4	1021	4	0	0
T5	3189	2	0	0
T6	1045	3	0	0
T7	1718	2	0	0
T8	2457	3	0	0
T9	1446	7	0	0
T10	1521	7	0	0