Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	2295595	5658	0	0
EscTimeoutStoppedByClReset_A	2295225	79532	0	0
EscTimeoutTriggersReset_A	304923	328	0	0
RomAllowActiveState_A	2295225	4115	0	0
RomAllowCheckGoodState_A	2295225	4165	0	0
RomBlockActiveState_A	2295225	26050	0	0
RomBlockCheckGoodState_A	2295225	18624	0	0
RomIntgChkDisFalse_A	2295225	2124514	0	0
RomIntgChkDisTrue_A	2295225	19112	0	0
RstreqChkEsctimeout_A	2295225	1053	0	0
RstreqChkFsmterm_A	2295225	120	0	0
RstreqChkGlbesc_A	2295225	1053	0	0
RstreqChkMainpd_A	2295225	53028	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2295595	5658	0	0
T11	2444	24	0	0
T12	14909	78	0	0
T13	15305	110	0	0
T16	945	0	0	0
T27	1957	0	0	0
T29	1463	0	0	0
T41	2436	0	0	0
T48	1270	0	0	0
T49	15547	174	0	0
T51	0	182	0	0
T97	1568	0	0	0
T134	0	217	0	0
T135	0	105	0	0
T136	0	93	0	0
T137	0	93	0	0
T138	0	58	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2295225	79532	0	0
T1	1836	59	0	0
T2	1378	43	0	0
T3	1502	51	0	0
T4	1021	1	0	0
T5	3189	13	0	0
T6	1045	12	0	0
T7	1718	24	0	0
T8	2457	11	0	0
T9	1446	30	0	0
T10	1521	97	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304923	328	0	0
T11	205	3	0	0
T12	599	3	0	0
T13	344	3	0	0
T16	330	0	0	0
T27	594	0	0	0
T29	474	0	0	0
T41	1581	0	0	0
T48	390	0	0	0
T49	208	2	0	0
T50	0	4	0	0
T51	0	2	0	0
T97	727	0	0	0
T134	0	3	0	0
T135	0	3	0	0
T136	0	2	0	0
T137	0	2	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2295225	4115	0	0
T1	1836	3	0	0
T2	1378	3	0	0
T3	1502	5	0	0
T4	1021	4	0	0
T5	3189	2	0	0
T6	1045	3	0	0
T7	1718	2	0	0
T8	2457	3	0	0
T9	1446	7	0	0
T10	1521	7	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2295225	4165	0	0
T1	1836	3	0	0
T2	1378	3	0	0
T3	1502	5	0	0
T4	1021	4	0	0
T5	3189	2	0	0
T6	1045	3	0	0
T7	1718	2	0	0
T8	2457	3	0	0
T9	1446	7	0	0
T10	1521	7	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2295225	26050	0	0
T10	1521	225	0	0
T11	2444	0	0	0
T12	14909	0	0	0
T13	15304	0	0	0
T14	3127	0	0	0
T15	2614	0	0	0
T16	945	0	0	0
T24	6720	0	0	0
T27	0	164	0	0
T28	0	42	0	0
T37	0	431	0	0
T38	0	152	0	0
T42	0	918	0	0
T46	0	936	0	0
T47	0	621	0	0
T48	1270	0	0	0
T49	15546	0	0	0
T139	0	73	0	0
T140	0	163	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2295225	18624	0	0
T10	1521	117	0	0
T11	2444	0	0	0
T12	14909	0	0	0
T13	15304	0	0	0
T14	3127	0	0	0
T15	2614	0	0	0
T16	945	0	0	0
T24	6720	0	0	0
T27	0	84	0	0
T28	0	7	0	0
T37	0	203	0	0
T38	0	51	0	0
T42	0	1094	0	0
T46	0	1074	0	0
T47	0	366	0	0
T48	1270	0	0	0
T49	15546	0	0	0
T140	0	85	0	0
T141	0	1061	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2295225	2124514	0	0
T1	1836	1786	0	0
T2	1378	1145	0	0
T3	1502	1135	0	0
T4	1021	681	0	0
T5	3189	3121	0	0
T6	1045	774	0	0
T7	1718	1550	0	0
T8	2457	2367	0	0
T9	1446	905	0	0
T10	1521	1176	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2295225	19112	0	0
T10	1521	157	0	0
T11	2444	0	0	0
T12	14909	0	0	0
T13	15304	0	0	0
T14	3127	0	0	0
T15	2614	0	0	0
T16	945	0	0	0
T24	6720	0	0	0
T27	0	74	0	0
T37	0	1059	0	0
T38	0	686	0	0
T42	0	1425	0	0
T46	0	295	0	0
T48	1270	0	0	0
T49	15546	0	0	0
T139	0	60	0	0
T140	0	901	0	0
T141	0	412	0	0
T142	0	280	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2295225	1053	0	0
T6	1045	2	0	0
T7	1718	1	0	0
T8	2457	0	0	0
T9	1446	0	0	0
T10	1521	2	0	0
T11	2444	1	0	0
T12	14909	1	0	0
T13	0	1	0	0
T14	3127	0	0	0
T15	2614	0	0	0
T24	6720	7	0	0
T27	0	3	0	0
T48	0	3	0	0
T49	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2295225	120	0	0
T18	20264	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T30	0	20	0	0
T31	0	40	0	0
T32	1762	0	0	0
T33	2300	0	0	0
T34	1304	0	0	0
T35	1324	0	0	0
T36	16280	0	0	0
T37	2672	0	0	0
T38	1541	0	0	0
T39	2820	0	0	0
T40	3311	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2295225	1053	0	0
T6	1045	2	0	0
T7	1718	1	0	0
T8	2457	0	0	0
T9	1446	0	0	0
T10	1521	2	0	0
T11	2444	1	0	0
T12	14909	1	0	0
T13	0	1	0	0
T14	3127	0	0	0
T15	2614	0	0	0
T24	6720	7	0	0
T27	0	3	0	0
T48	0	3	0	0
T49	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2295225	53028	0	0
T2	1378	12	0	0
T3	1502	0	0	0
T4	1021	11	0	0
T5	3189	0	0	0
T6	1045	0	0	0
T7	1718	0	0	0
T8	2457	0	0	0
T9	1446	28	0	0
T10	1521	47	0	0
T14	3127	0	0	0
T24	0	985	0	0
T27	0	116	0	0
T28	0	34	0	0
T41	0	131	0	0
T97	0	21	0	0
T98	0	5	0	0