PWRMGR Simulation Results

Monday July 29 2024 23:02:32 UTC

GitHub Revision: `39f3866b56`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 91682663165753342493852681547271085771042321116470426223748766059309541455602

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.730s	29.567us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.700s	44.423us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.730s	21.238us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.320s	325.317us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.970s	39.977us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.410s	51.420us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.730s	21.238us	20	20	100.00
		pwrmgr_csr_aliasing	0.970s	39.977us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	0.890s	120.241us	7	50	14.00
V2	control_clks	pwrmgr_wakeup	0.890s	120.241us	7	50	14.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.210s	35.790us	50	50	100.00
		pwrmgr_lowpower_invalid	0.860s	45.311us	50	50	100.00
V2	reset	pwrmgr_reset	0.890s	70.267us	50	50	100.00
		pwrmgr_reset_invalid	1.070s	90.937us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	0.890s	70.267us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	0.800s	72.755us	3	50	6.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	0.820s	69.879us	6	50	12.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.880s	60.801us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	1.320s	125.486us	2	50	4.00
V2	intr_test	pwrmgr_intr_test	0.670s	48.509us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.970s	492.452us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.970s	492.452us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.700s	44.423us	5	5	100.00
		pwrmgr_csr_rw	0.730s	21.238us	20	20	100.00
		pwrmgr_csr_aliasing	0.970s	39.977us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.900s	43.785us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.700s	44.423us	5	5	100.00
		pwrmgr_csr_rw	0.730s	21.238us	20	20	100.00
		pwrmgr_csr_aliasing	0.970s	39.977us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.900s	43.785us	20	20	100.00
V2		TOTAL			358	540	66.30
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.830s	294.625us	20	20	100.00
		pwrmgr_sec_cm	2.130s	636.097us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.130s	636.097us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.130s	636.097us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.830s	294.625us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	0.740s	71.141us	0	50	0.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	0.760s	49.832us	0	50	0.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.920s	97.033us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.690s	28.816us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.130s	636.097us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.130s	636.097us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.130s	636.097us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.680s	34.194us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.720s	48.311us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.090s	135.352us	7	50	14.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.730s	21.238us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.730s	21.238us	20	20	100.00
V2S		TOTAL			232	375	61.87
V3	escalation_timeout	pwrmgr_escalation_timeout	1.030s	166.885us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	2.030s	302.968us	0	50	0.00
V3		TOTAL			50	100	50.00
		TOTAL			745	1120	66.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	8	66.67
V2S	9	9	6	66.67
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.39	98.23	96.15	99.44	96.00	96.18	100.00	95.74

Failure Buckets

UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*])

has 100 failures:

Test pwrmgr_sec_cm_lc_ctrl_intersig_mubi has 50 failures.

0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.93028317080218456526493176682047436765908061309861288867411838215779790292391
Line 261, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log

  UVM_ERROR @  28821197 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  28821197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.61900689933334301497378991214337891494615864880126342125409160014460121969867
Line 261, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log

  UVM_ERROR @  22657752 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  22657752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 48 more failures.

Test pwrmgr_sec_cm_rom_ctrl_intersig_mubi has 50 failures.

0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.95803170873946766997218851267522529605925541271683666122184505714842415473224
Line 266, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest/run.log

  UVM_ERROR @  26030678 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  26030678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.9716135963965348044410459568114384328474809486300227305190654709762624529725
Line 264, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest/run.log

  UVM_ERROR @  25170873 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  25170873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 48 more failures.

UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*])

has 86 failures:

Test pwrmgr_stress_all_with_rand_reset has 19 failures.

0.pwrmgr_stress_all_with_rand_reset.36964553962215466833976123080983513095527796833899130990395056176537636226238
Line 268, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  26275728 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  26275728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.pwrmgr_stress_all_with_rand_reset.10474015897118965026720023408893227037304744272461703619260293139033578679918
Line 365, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  92861998 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  92861998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 17 more failures.

Test pwrmgr_stress_all has 20 failures.

0.pwrmgr_stress_all.64360795898375572074545933088257997922245597465440638270502672936394538330227
Line 329, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @ 148159582 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 148159582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.pwrmgr_stress_all.80578107065380434378546632441805536284409509122618807826287326449579834305016
Line 262, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @  27810178 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  27810178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 18 more failures.

Test pwrmgr_wakeup_reset has 47 failures.

1.pwrmgr_wakeup_reset.42099771004995098369552656149343769469770427046466562596555877143854161332565
Line 266, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_wakeup_reset/latest/run.log

  UVM_ERROR @  21083594 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  21083594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.pwrmgr_wakeup_reset.10628959268773199975715966963586739029802255158807279902614427883356830430371
Line 269, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_wakeup_reset/latest/run.log

  UVM_ERROR @  19854488 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  19854488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 45 more failures.

UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*])

has 51 failures:

Test pwrmgr_lowpower_wakeup_race has 33 failures.

2.pwrmgr_lowpower_wakeup_race.72549636009517798076460295795397962664255882150754249699025942934695485780505
Line 305, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_lowpower_wakeup_race/latest/run.log

  UVM_ERROR @ 108624592 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 108624592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.pwrmgr_lowpower_wakeup_race.46118903289292875759605991015674401274394508884900202481826135555748151839344
Line 267, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_lowpower_wakeup_race/latest/run.log

  UVM_ERROR @  37785842 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  37785842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 31 more failures.

Test pwrmgr_stress_all has 9 failures.

2.pwrmgr_stress_all.44608863431768373571574997602061570394469524805045513786979748411366699813038
Line 348, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @ 162207231 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 162207231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.pwrmgr_stress_all.100873323024821453744863433867861309550254405580804852323076677377349359431184
Line 277, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @  37504452 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  37504452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test pwrmgr_stress_all_with_rand_reset has 9 failures.

9.pwrmgr_stress_all_with_rand_reset.85336966900312001513036592403580613325195091324476453413633536480479185405770
Line 257, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  35649597 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  35649597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.pwrmgr_stress_all_with_rand_reset.28151987969227029024563260273030705329440568938195841340097700227655188423229
Line 341, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 186826483 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 186826483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*])

has 50 failures:

Test pwrmgr_wakeup has 27 failures.

0.pwrmgr_wakeup.56388261710234604839698607060339807408690999119858086930966345408072953973621
Line 314, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_wakeup/latest/run.log

  UVM_ERROR @  75475221 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  75475221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.pwrmgr_wakeup.27750850419009356366304463174122205117808748025253574535436901083575666496461
Line 266, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_wakeup/latest/run.log

  UVM_ERROR @  24094788 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  24094788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 25 more failures.

Test pwrmgr_stress_all_with_rand_reset has 12 failures.

1.pwrmgr_stress_all_with_rand_reset.11242020234484269612182719102952607862317730231694884363071466562572774845049
Line 339, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  70850042 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  70850042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.pwrmgr_stress_all_with_rand_reset.99466380722343313902151295533920808003135496029282160437849433418189493219364
Line 284, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  29178816 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  29178816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 10 more failures.

Test pwrmgr_stress_all has 11 failures.

3.pwrmgr_stress_all.77580129626383500590543430960873544275249474187348251312045786570058833534742
Line 282, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @  30751820 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  30751820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.pwrmgr_stress_all.67314940141121485292299282700842186650312783545528057748413994468140805143054
Line 258, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @  36317123 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  36317123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_sec_cm_ctrl_config_regwen_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 31 failures:
- Test pwrmgr_sec_cm_ctrl_config_regwen has 31 failures.
  - 4.pwrmgr_sec_cm_ctrl_config_regwen.61214050845761643695639464910107728548973083947596092991213407125784469325620
    Line 257, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log
```
  UVM_ERROR @  27311722 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_sec_cm_ctrl_config_regwen_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  27311722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.pwrmgr_sec_cm_ctrl_config_regwen.42888782843806813807604761703978837966940385746581807694067572612885061887471
    Line 308, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log
```
  UVM_ERROR @  49227252 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_sec_cm_ctrl_config_regwen_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  49227252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 29 more failures.

UVM_FATAL (pwrmgr_base_vseq.sv:721) [pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} actual:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}}

has 25 failures:

Test pwrmgr_wakeup has 16 failures.

1.pwrmgr_wakeup.47921481415479844049008064127955638157010921833147377363323518354500933916333
Line 280, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_wakeup/latest/run.log

  UVM_FATAL @ 150303039 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h2d}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @ 150303039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.pwrmgr_wakeup.88197452024704763882336513968910444632861042617911121657413752916606042678142
Line 283, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_wakeup/latest/run.log

  UVM_FATAL @  64930428 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h0}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @  64930428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 14 more failures.

Test pwrmgr_stress_all_with_rand_reset has 6 failures.

3.pwrmgr_stress_all_with_rand_reset.52411595631509353678197581164986254078922888098256614740595436432359218154353
Line 280, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @  57902248 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h2}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @  57902248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.pwrmgr_stress_all_with_rand_reset.57907702165325671844277054034156710634301546961240908775039436550310724121745
Line 310, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 109512202 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h1e}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @ 109512202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test pwrmgr_stress_all has 3 failures.

11.pwrmgr_stress_all.12582229154683759202706476148942762170854924048686979642150003820480097566276
Line 340, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_stress_all/latest/run.log

  UVM_FATAL @ 106974207 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h0}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @ 106974207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

38.pwrmgr_stress_all.19734305336082670045658377035635844535346785748018342246908597509143683542053
Line 396, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/38.pwrmgr_stress_all/latest/run.log

  UVM_FATAL @ 201600506 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h25}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @ 201600506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (pwrmgr_base_vseq.sv:721) [pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} actual:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}}

has 20 failures:

Test pwrmgr_lowpower_wakeup_race has 11 failures.

0.pwrmgr_lowpower_wakeup_race.1908052364949914543610821250516937942844653350254340429130880312408649644706
Line 283, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_lowpower_wakeup_race/latest/run.log

  UVM_FATAL @  51546901 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h22}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @  51546901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.pwrmgr_lowpower_wakeup_race.38238406486992940614635615247778563450995443662177067915798550504078235513103
Line 266, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_lowpower_wakeup_race/latest/run.log

  UVM_FATAL @ 112061732 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h5}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @ 112061732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

Test pwrmgr_stress_all_with_rand_reset has 4 failures.

5.pwrmgr_stress_all_with_rand_reset.70999797334704836001806410026965932701414885719454592311156266209708350642312
Line 355, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 241913008 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h6}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @ 241913008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.pwrmgr_stress_all_with_rand_reset.101323715926980839053709400075488082920500174166967112662990741970756476489611
Line 272, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/14.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @  85392704 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h24}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @  85392704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test pwrmgr_stress_all has 5 failures.

6.pwrmgr_stress_all.69370058087093395196507282164623527419550749092528090524748169325423640877426
Line 259, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_stress_all/latest/run.log

  UVM_FATAL @  58865614 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'hd}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @  58865614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.pwrmgr_stress_all.18340192699840232355635352269167037664710008640304768262638540306136875120206
Line 280, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_stress_all/latest/run.log

  UVM_FATAL @  84023721 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h24}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @  84023721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (pwrmgr_base_vseq.sv:721) [pwrmgr_sec_cm_ctrl_config_regwen_vseq] wake info wait timeout exp:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} actual:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}}

has 12 failures:

Test pwrmgr_sec_cm_ctrl_config_regwen has 12 failures.

3.pwrmgr_sec_cm_ctrl_config_regwen.112143564846081219449545350857556145681136331688265021942952996948727374971261
Line 293, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log

  UVM_FATAL @  79696310 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_sec_cm_ctrl_config_regwen_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h20}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @  79696310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.pwrmgr_sec_cm_ctrl_config_regwen.61633817212482093319063711981469188708501587616853148057634640015111490023252
Line 319, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log

  UVM_FATAL @  82725976 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_sec_cm_ctrl_config_regwen_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h21}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @  82725976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 10 more failures.