a47820eb4c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwrmgr_smoke | 0.710s | 33.101us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pwrmgr_csr_hw_reset | 0.750s | 32.851us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwrmgr_csr_rw | 0.700s | 20.776us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwrmgr_csr_bit_bash | 3.210s | 612.786us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwrmgr_csr_aliasing | 1.040s | 54.647us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwrmgr_csr_mem_rw_with_rand_reset | 1.170s | 119.247us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwrmgr_csr_rw | 0.700s | 20.776us | 20 | 20 | 100.00 |
| pwrmgr_csr_aliasing | 1.040s | 54.647us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | wakeup | pwrmgr_wakeup | 0.900s | 67.511us | 3 | 50 | 6.00 |
| V2 | control_clks | pwrmgr_wakeup | 0.900s | 67.511us | 3 | 50 | 6.00 |
| V2 | aborted_low_power | pwrmgr_aborted_low_power | 1.110s | 45.482us | 50 | 50 | 100.00 |
| pwrmgr_lowpower_invalid | 0.790s | 45.306us | 50 | 50 | 100.00 | ||
| V2 | reset | pwrmgr_reset | 0.940s | 77.316us | 50 | 50 | 100.00 |
| pwrmgr_reset_invalid | 1.130s | 109.464us | 50 | 50 | 100.00 | ||
| V2 | main_power_glitch_reset | pwrmgr_reset | 0.940s | 77.316us | 50 | 50 | 100.00 |
| V2 | reset_wakeup_race | pwrmgr_wakeup_reset | 0.790s | 62.123us | 3 | 50 | 6.00 |
| V2 | lowpower_wakeup_race | pwrmgr_lowpower_wakeup_race | 1.020s | 106.878us | 4 | 50 | 8.00 |
| V2 | disable_rom_integrity_check | pwrmgr_disable_rom_integrity_check | 0.860s | 57.926us | 50 | 50 | 100.00 |
| V2 | stress_all | pwrmgr_stress_all | 1.220s | 100.575us | 1 | 50 | 2.00 |
| V2 | intr_test | pwrmgr_intr_test | 0.690s | 169.598us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pwrmgr_tl_errors | 2.640s | 528.730us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwrmgr_tl_errors | 2.640s | 528.730us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwrmgr_csr_hw_reset | 0.750s | 32.851us | 5 | 5 | 100.00 |
| pwrmgr_csr_rw | 0.700s | 20.776us | 20 | 20 | 100.00 | ||
| pwrmgr_csr_aliasing | 1.040s | 54.647us | 5 | 5 | 100.00 | ||
| pwrmgr_same_csr_outstanding | 0.970s | 164.307us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwrmgr_csr_hw_reset | 0.750s | 32.851us | 5 | 5 | 100.00 |
| pwrmgr_csr_rw | 0.700s | 20.776us | 20 | 20 | 100.00 | ||
| pwrmgr_csr_aliasing | 1.040s | 54.647us | 5 | 5 | 100.00 | ||
| pwrmgr_same_csr_outstanding | 0.970s | 164.307us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 351 | 540 | 65.00 | |||
| V2S | tl_intg_err | pwrmgr_tl_intg_err | 2.130s | 2.185ms | 20 | 20 | 100.00 |
| pwrmgr_sec_cm | 2.320s | 653.895us | 5 | 5 | 100.00 | ||
| V2S | prim_count_check | pwrmgr_sec_cm | 2.320s | 653.895us | 5 | 5 | 100.00 |
| V2S | prim_fsm_check | pwrmgr_sec_cm | 2.320s | 653.895us | 5 | 5 | 100.00 |
| V2S | sec_cm_bus_integrity | pwrmgr_tl_intg_err | 2.130s | 2.185ms | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_ctrl_intersig_mubi | pwrmgr_sec_cm_lc_ctrl_intersig_mubi | 0.840s | 79.902us | 0 | 50 | 0.00 |
| V2S | sec_cm_rom_ctrl_intersig_mubi | pwrmgr_sec_cm_rom_ctrl_intersig_mubi | 0.870s | 84.085us | 0 | 50 | 0.00 |
| V2S | sec_cm_rstmgr_intersig_mubi | pwrmgr_sec_cm_rstmgr_intersig_mubi | 0.980s | 73.445us | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_rx_clk_bkgn_chk | pwrmgr_esc_clk_rst_malfunc | 0.680s | 28.915us | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_rx_clk_local_esc | pwrmgr_sec_cm | 2.320s | 653.895us | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | pwrmgr_sec_cm | 2.320s | 653.895us | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_terminal | pwrmgr_sec_cm | 2.320s | 653.895us | 5 | 5 | 100.00 |
| V2S | sec_cm_ctrl_flow_global_esc | pwrmgr_global_esc | 0.700s | 59.959us | 50 | 50 | 100.00 |
| V2S | sec_cm_main_pd_rst_local_esc | pwrmgr_glitch | 0.730s | 62.449us | 50 | 50 | 100.00 |
| V2S | sec_cm_ctrl_config_regwen | pwrmgr_sec_cm_ctrl_config_regwen | 0.890s | 55.867us | 6 | 50 | 12.00 |
| V2S | sec_cm_wakeup_config_regwen | pwrmgr_csr_rw | 0.700s | 20.776us | 20 | 20 | 100.00 |
| V2S | sec_cm_reset_config_regwen | pwrmgr_csr_rw | 0.700s | 20.776us | 20 | 20 | 100.00 |
| V2S | TOTAL | 231 | 375 | 61.60 | |||
| V3 | escalation_timeout | pwrmgr_escalation_timeout | 1.060s | 315.549us | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | pwrmgr_stress_all_with_rand_reset | 1.780s | 207.901us | 0 | 50 | 0.00 |
| V3 | TOTAL | 50 | 100 | 50.00 | |||
| TOTAL | 737 | 1120 | 65.80 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 12 | 12 | 8 | 66.67 |
| V2S | 9 | 9 | 6 | 66.67 |
| V3 | 2 | 2 | 1 | 50.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.44 | 98.23 | 96.15 | 99.44 | 96.00 | 96.18 | 100.00 | 96.07 |
UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 100 failures:
0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.50975406894781025987526044360344466594557020754192340879295015485915798722632
Line 271, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log
UVM_ERROR @ 21263431 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 21263431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.30381838402381924184065892238318885977283282048156372432675757134918312624726
Line 262, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log
UVM_ERROR @ 30985016 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 30985016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.57639350377075760673986806606201290488412189358557464516213874823513494451767
Line 262, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest/run.log
UVM_ERROR @ 46091139 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 46091139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.92480918675015543152298501006687765636413015776729143364440524335291893246419
Line 271, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest/run.log
UVM_ERROR @ 23026653 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 23026653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 74 failures:
0.pwrmgr_wakeup_reset.56031346646679827187166602482155621003882871233134139647943993378747653198490
Line 262, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_wakeup_reset/latest/run.log
UVM_ERROR @ 31029208 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 31029208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.pwrmgr_wakeup_reset.23463364260458316925622624147821617346889331073447882177336911787875610454557
Line 261, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_wakeup_reset/latest/run.log
UVM_ERROR @ 31840696 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 31840696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 45 more failures.
0.pwrmgr_stress_all.62576891942518241663864705257007647096964043080793123244276537704488016571270
Line 323, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 114930029 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 114930029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.pwrmgr_stress_all.97315841932874513180217144823664435536649597130672335295941681213245374699496
Line 505, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 357956924 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 357956924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
3.pwrmgr_stress_all_with_rand_reset.104640959332616264126252563854554160191193220640012099432444270193820925481659
Line 270, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 39055788 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 39055788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.pwrmgr_stress_all_with_rand_reset.39682358146252239407617277392655497853619417415946835871154782932501527119150
Line 532, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 350828878 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 350828878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 61 failures:
0.pwrmgr_wakeup.10128595976028984233259087022235923347551046545580529523632345112854198525624
Line 258, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_wakeup/latest/run.log
UVM_ERROR @ 32613232 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 32613232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.pwrmgr_wakeup.13479959566161245998213540282238175192556444619601956841559981211783697834882
Line 259, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_wakeup/latest/run.log
UVM_ERROR @ 79041659 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 79041659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 35 more failures.
0.pwrmgr_stress_all_with_rand_reset.42260037478241553701104820156681264817044503154467639892699988602503479538340
Line 261, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 58571653 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 58571653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.pwrmgr_stress_all_with_rand_reset.46233751978828747724179755132598074369995920824655181897807541598050717682225
Line 433, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 237442923 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 237442923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
2.pwrmgr_stress_all.6236728177679242516308656988659114609207270186632247997233164820598584498181
Line 331, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 52558615 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 52558615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.pwrmgr_stress_all.21507023804856073623329677221552109437513422003815224937498182301708935232799
Line 272, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 81918302 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 81918302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 60 failures:
0.pwrmgr_lowpower_wakeup_race.19376458848130059277055305312084411455684786155401211096459019050081159042152
Line 264, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_lowpower_wakeup_race/latest/run.log
UVM_ERROR @ 55314291 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 55314291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.pwrmgr_lowpower_wakeup_race.20620498080777684355194005469483306642845183897299898577541972856550502627658
Line 260, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_lowpower_wakeup_race/latest/run.log
UVM_ERROR @ 53692819 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 53692819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 30 more failures.
1.pwrmgr_stress_all_with_rand_reset.24112520409942209800528792832815554534044591484688576609058051917344464368753
Line 645, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 207901339 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 207901339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.pwrmgr_stress_all_with_rand_reset.92477536658164079964214377188484484717093458497620313777898115646575083061419
Line 282, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 30262373 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 30262373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
3.pwrmgr_stress_all.22259287803794243147925454863393485877962665444100234293416959654909404552779
Line 261, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 43474938 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 43474938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.pwrmgr_stress_all.105552531034521471305598401236756772739627233222625064194353901504517405781878
Line 272, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 30721314 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 30721314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_sec_cm_ctrl_config_regwen_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 33 failures:
0.pwrmgr_sec_cm_ctrl_config_regwen.112282110912120435436349988006946746307718093708885810888918738210439437833943
Line 270, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log
UVM_ERROR @ 54983731 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_sec_cm_ctrl_config_regwen_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 54983731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.pwrmgr_sec_cm_ctrl_config_regwen.73349021465643401143455306318108028162177677677428197311602045535538543878796
Line 272, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log
UVM_ERROR @ 25816893 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_sec_cm_ctrl_config_regwen_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 25816893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 31 more failures.
UVM_FATAL (pwrmgr_base_vseq.sv:721) [pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} actual:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} has 22 failures:
3.pwrmgr_wakeup.40791940794964133987791393937185719098296922042248848875069162894416217571647
Line 280, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_wakeup/latest/run.log
UVM_FATAL @ 68142944 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h8}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 68142944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.pwrmgr_wakeup.53371954801350513817385322292496647940797227917665165853584433977280127439528
Line 269, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_wakeup/latest/run.log
UVM_FATAL @ 64921650 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h28}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 64921650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
8.pwrmgr_stress_all_with_rand_reset.75781740120480299206300366731980870356965997906318869194636502040975583551777
Line 295, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 86064072 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'hc}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 86064072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.pwrmgr_stress_all_with_rand_reset.74194804441515397497563180869650769057173589328482785021886592773879172622474
Line 276, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 56069279 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h20}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 56069279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
15.pwrmgr_stress_all.67510342009759657490793822231711816326297466708882889689688528478661393260079
Line 402, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_stress_all/latest/run.log
UVM_FATAL @ 131517605 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h5}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 131517605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.pwrmgr_stress_all.99617752818044354971776830843071906857798451503887875613113582692409423514034
Line 452, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/31.pwrmgr_stress_all/latest/run.log
UVM_FATAL @ 225583179 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h21}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 225583179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (pwrmgr_base_vseq.sv:721) [pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} actual:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} has 22 failures:
6.pwrmgr_lowpower_wakeup_race.85754327121623856465629483505457646408682607764912260692320449367714980194874
Line 284, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_lowpower_wakeup_race/latest/run.log
UVM_FATAL @ 49997403 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h0}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 49997403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.pwrmgr_lowpower_wakeup_race.46671759382797314696001966014992017499357955507915715437968518936851720115338
Line 263, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_lowpower_wakeup_race/latest/run.log
UVM_FATAL @ 54302901 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h1b}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 54302901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
21.pwrmgr_stress_all.32902265069198715801710636508629800943776626188533221811989796868328508308862
Line 265, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/21.pwrmgr_stress_all/latest/run.log
UVM_FATAL @ 52305995 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h0}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 52305995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.pwrmgr_stress_all.1354713968381222583932083410544895459601904593446805320400582268735213692713
Line 373, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/25.pwrmgr_stress_all/latest/run.log
UVM_FATAL @ 272356865 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h38}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 272356865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
39.pwrmgr_stress_all_with_rand_reset.97028220944025451993059751337289934275912523230221047285772781163915097966740
Line 380, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/39.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 216673492 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h0}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 216673492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.pwrmgr_stress_all_with_rand_reset.3278965438529576118880792570870992570374241701362829197365075834764206183151
Line 351, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/41.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 84014490 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'ha}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 84014490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (pwrmgr_base_vseq.sv:721) [pwrmgr_sec_cm_ctrl_config_regwen_vseq] wake info wait timeout exp:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} actual:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} has 11 failures:
4.pwrmgr_sec_cm_ctrl_config_regwen.91493034458612186246203436591556518017391808402141943139534422197868064174728
Line 298, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log
UVM_FATAL @ 88511391 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_sec_cm_ctrl_config_regwen_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h30}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 88511391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.pwrmgr_sec_cm_ctrl_config_regwen.38014006260962389335246559273462651321885413545956582952170464550389644296865
Line 265, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log
UVM_FATAL @ 51959746 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_sec_cm_ctrl_config_regwen_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h1}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 51959746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.