Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38229	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

27771

1

T1

12

T2

26

T5

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	33615	1			T1	21		T2	56		T3	1
values[0x0]	16088	1			T1	6		T2	5		T5	18
values[0x1]	16297	1			T1	10		T2	6		T4	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	30894	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

35106

1

T1

19

T2

32

T5

26

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	259	1			T51	1		T81	2		T42	1
valid_sources[0x01]	180	1			T207	4		T94	2		T208	1
valid_sources[0x02]	183	1			T2	2		T7	1		T11	1
valid_sources[0x03]	361	1			T5	2		T7	1		T51	3
valid_sources[0x04]	239	1			T2	2		T41	1		T51	1
valid_sources[0x05]	376	1			T51	2		T81	1		T12	1
valid_sources[0x06]	212	1			T46	6		T42	1		T209	1
valid_sources[0x07]	202	1			T45	3		T210	3		T211	1
valid_sources[0x08]	365	1			T46	6		T81	1		T43	1
valid_sources[0x09]	327	1			T7	2		T11	2		T15	1
valid_sources[0x0a]	169	1			T92	2		T14	2		T26	1
valid_sources[0x0b]	375	1			T7	2		T41	1		T51	1
valid_sources[0x0c]	259	1			T7	2		T14	1		T212	1
valid_sources[0x0d]	454	1			T2	1		T46	1		T41	2
valid_sources[0x0e]	211	1			T81	3		T12	3		T15	1
valid_sources[0x0f]	213	1			T7	5		T46	3		T92	3
valid_sources[0x10]	373	1			T1	1		T5	1		T7	6
valid_sources[0x11]	202	1			T7	3		T41	2		T11	1
valid_sources[0x12]	215	1			T46	3		T12	1		T43	1
valid_sources[0x13]	164	1			T7	1		T51	1		T26	1
valid_sources[0x14]	306	1			T10	2		T12	1		T27	20
valid_sources[0x15]	380	1			T2	2		T7	1		T81	1
valid_sources[0x16]	238	1			T46	1		T82	1		T213	3
valid_sources[0x17]	253	1			T5	1		T81	1		T11	1
valid_sources[0x18]	167	1			T2	1		T11	2		T82	1
valid_sources[0x19]	195	1			T2	2		T81	2		T43	1
valid_sources[0x1a]	155	1			T5	2		T7	1		T46	1
valid_sources[0x1b]	186	1			T51	1		T81	2		T12	1
valid_sources[0x1c]	227	1			T5	1		T10	1		T81	3
valid_sources[0x1d]	239	1			T41	1		T51	1		T81	1
valid_sources[0x1e]	167	1			T41	1		T11	1		T212	1
valid_sources[0x1f]	247	1			T5	2		T7	1		T81	2
valid_sources[0x20]	208	1			T2	6		T7	1		T46	3
valid_sources[0x21]	205	1			T42	1		T14	1		T15	1
valid_sources[0x22]	130	1			T5	3		T15	1		T212	1
valid_sources[0x23]	340	1			T2	2		T10	3		T41	1
valid_sources[0x24]	176	1			T5	1		T42	1		T15	3
valid_sources[0x25]	329	1			T81	1		T42	1		T14	2
valid_sources[0x26]	157	1			T46	1		T51	2		T12	1
valid_sources[0x27]	209	1			T10	1		T46	1		T81	1
valid_sources[0x28]	288	1			T16	5		T46	2		T41	1
valid_sources[0x29]	308	1			T5	1		T10	1		T12	1
valid_sources[0x2a]	211	1			T1	1		T7	1		T41	1
valid_sources[0x2b]	314	1			T92	2		T28	4		T15	1
valid_sources[0x2c]	486	1			T5	1		T14	1		T15	2
valid_sources[0x2d]	202	1			T5	1		T7	1		T81	1
valid_sources[0x2e]	189	1			T5	1		T51	1		T13	3
valid_sources[0x2f]	303	1			T8	1		T46	2		T41	1
valid_sources[0x30]	190	1			T5	1		T51	2		T11	1
valid_sources[0x31]	192	1			T9	1		T14	1		T15	1
valid_sources[0x32]	236	1			T46	1		T41	2		T51	2
valid_sources[0x33]	790	1			T82	2		T45	2		T14	1
valid_sources[0x34]	173	1			T1	3		T10	3		T51	1
valid_sources[0x35]	561	1			T7	1		T10	1		T41	1
valid_sources[0x36]	230	1			T5	1		T12	1		T13	3
valid_sources[0x37]	188	1			T7	1		T10	2		T42	2
valid_sources[0x38]	204	1			T1	3		T2	1		T7	1
valid_sources[0x39]	227	1			T7	2		T11	1		T45	1
valid_sources[0x3a]	261	1			T2	1		T7	1		T12	1
valid_sources[0x3b]	240	1			T42	1		T12	1		T14	1
valid_sources[0x3c]	192	1			T27	2		T14	1		T213	1
valid_sources[0x3d]	313	1			T46	1		T43	1		T45	1
valid_sources[0x3e]	397	1			T41	1		T55	1		T213	1
valid_sources[0x3f]	298	1			T5	2		T10	1		T41	1
valid_sources[0x40]	278	1			T41	1		T42	2		T82	1
valid_sources[0x41]	323	1			T46	1		T41	1		T92	1
valid_sources[0x42]	200	1			T7	1		T46	7		T81	4
valid_sources[0x43]	235	1			T2	1		T7	2		T15	1
valid_sources[0x44]	182	1			T26	2		T94	8		T55	1
valid_sources[0x45]	295	1			T42	1		T11	1		T15	1
valid_sources[0x46]	278	1			T81	1		T43	3		T212	1
valid_sources[0x47]	384	1			T7	2		T15	1		T211	1
valid_sources[0x48]	173	1			T2	1		T5	1		T10	2
valid_sources[0x49]	392	1			T41	2		T51	4		T81	5
valid_sources[0x4a]	287	1			T7	1		T81	2		T82	1
valid_sources[0x4b]	234	1			T13	24		T83	1		T14	1
valid_sources[0x4c]	242	1			T46	6		T41	2		T15	1
valid_sources[0x4d]	285	1			T5	1		T43	1		T82	1
valid_sources[0x4e]	209	1			T7	1		T14	4		T26	1
valid_sources[0x4f]	407	1			T5	1		T46	3		T82	1
valid_sources[0x50]	209	1			T7	1		T43	1		T15	1
valid_sources[0x51]	197	1			T2	1		T81	1		T48	1
valid_sources[0x52]	318	1			T41	1		T92	1		T26	4
valid_sources[0x53]	396	1			T1	2		T51	1		T81	5
valid_sources[0x54]	471	1			T82	1		T14	1		T15	1
valid_sources[0x55]	534	1			T2	1		T46	2		T51	1
valid_sources[0x56]	186	1			T5	1		T7	3		T12	1
valid_sources[0x57]	153	1			T81	1		T15	1		T212	1
valid_sources[0x58]	218	1			T51	1		T81	2		T42	1
valid_sources[0x59]	185	1			T46	1		T47	1		T81	1
valid_sources[0x5a]	359	1			T46	1		T11	1		T43	2
valid_sources[0x5b]	179	1			T2	1		T46	2		T207	2
valid_sources[0x5c]	216	1			T10	1		T46	6		T67	1
valid_sources[0x5d]	208	1			T5	2		T46	2		T51	1
valid_sources[0x5e]	227	1			T7	1		T81	1		T15	2
valid_sources[0x5f]	199	1			T7	2		T51	1		T81	1
valid_sources[0x60]	218	1			T5	1		T10	1		T11	2
valid_sources[0x61]	191	1			T7	3		T81	1		T42	1
valid_sources[0x62]	348	1			T81	2		T92	1		T212	3
valid_sources[0x63]	188	1			T43	1		T82	1		T14	1
valid_sources[0x64]	226	1			T46	2		T81	1		T42	1
valid_sources[0x65]	229	1			T7	1		T46	5		T81	2
valid_sources[0x66]	233	1			T1	2		T5	1		T7	1
valid_sources[0x67]	350	1			T7	2		T46	2		T11	2
valid_sources[0x68]	189	1			T5	1		T46	1		T15	1
valid_sources[0x69]	305	1			T2	1		T46	1		T41	1
valid_sources[0x6a]	292	1			T14	3		T15	1		T26	1
valid_sources[0x6b]	406	1			T7	1		T46	1		T81	1
valid_sources[0x6c]	194	1			T16	3		T46	1		T41	1
valid_sources[0x6d]	169	1			T51	1		T42	1		T43	1
valid_sources[0x6e]	238	1			T1	1		T46	2		T67	4
valid_sources[0x6f]	366	1			T7	3		T41	1		T67	1
valid_sources[0x70]	629	1			T7	1		T46	3		T81	1
valid_sources[0x71]	148	1			T212	1		T55	1		T170	1
valid_sources[0x72]	266	1			T7	1		T46	1		T42	1
valid_sources[0x73]	302	1			T5	1		T7	3		T82	1
valid_sources[0x74]	193	1			T2	1		T81	1		T42	1
valid_sources[0x75]	209	1			T51	1		T81	2		T82	1
valid_sources[0x76]	272	1			T2	4		T7	2		T46	3
valid_sources[0x77]	227	1			T81	1		T82	2		T45	1
valid_sources[0x78]	222	1			T2	2		T7	1		T10	1
valid_sources[0x79]	215	1			T41	2		T51	3		T81	1
valid_sources[0x7a]	250	1			T46	1		T14	1		T15	1
valid_sources[0x7b]	188	1			T7	1		T41	1		T15	2
valid_sources[0x7c]	197	1			T81	1		T29	1		T26	2
valid_sources[0x7d]	242	1			T212	1		T135	9		T208	4
valid_sources[0x7e]	230	1			T5	1		T10	2		T41	1
valid_sources[0x7f]	181	1			T41	1		T81	3		T12	1
valid_sources[0x80]	481	1			T81	2		T42	1		T12	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14289

1

T1

9

T2

23

T5

12

values[0x0]

all_enables

biggest_size

7822

1

T1

1

T2

2

T5

5

values[0x1]

all_enables

biggest_size

5660

1

T1

2

T2

1

T5

1