Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2744661	10761	0	0
intr_enable_rd_A	2744661	2649	0	0
reset_en_rd_A	2744661	1112	0	0
reset_en_regwen_rd_A	2744661	1108	0	0
wake_info_capture_dis_rd_A	2744661	1090	0	0
wakeup_en_rd_A	2744661	1500	0	0
wakeup_en_regwen_rd_A	2744661	1173	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2744661	10761	0	0
T22	5065	6	0	0
T23	13349	9	0	0
T24	4547	75	0	0
T56	6192	6	0	0
T57	3941	4	0	0
T58	5910	407	0	0
T59	1341	15	0	0
T60	8901	584	0	0
T77	2538	52	0	0
T93	4049	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2744661	2649	0	0
T11	1552	0	0	0
T12	2244	0	0	0
T18	3341	0	0	0
T42	5172	0	0	0
T43	4964	0	0	0
T48	667	0	0	0
T49	788	0	0	0
T51	3129	0	0	0
T55	0	46	0	0
T65	1953	2	0	0
T66	0	3	0	0
T81	2781	0	0	0
T83	0	8	0	0
T85	0	5	0	0
T86	0	54	0	0
T123	0	1	0	0
T124	0	5	0	0
T125	0	4	0	0
T126	0	83	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2744661	1112	0	0
T58	5910	15	0	0
T59	1341	1	0	0
T60	8901	15	0	0
T63	2483	22	0	0
T77	2538	8	0	0
T99	1764	7	0	0
T116	3865	36	0	0
T117	2356	51	0	0
T121	2768	28	0	0
T122	2560	13	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2744661	1108	0	0
T58	5910	5	0	0
T59	1341	9	0	0
T60	8901	15	0	0
T63	2483	10	0	0
T77	2538	11	0	0
T99	1764	2	0	0
T116	3865	43	0	0
T117	2356	2	0	0
T121	2768	21	0	0
T122	2560	33	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2744661	1090	0	0
T58	5910	20	0	0
T59	1341	4	0	0
T60	8901	8	0	0
T63	2483	36	0	0
T77	2538	4	0	0
T116	3865	37	0	0
T117	2356	12	0	0
T121	2768	4	0	0
T122	2560	23	0	0
T127	3317	14	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2744661	1500	0	0
T58	5910	7	0	0
T59	1341	28	0	0
T60	8901	16	0	0
T63	2483	14	0	0
T77	2538	7	0	0
T99	1764	9	0	0
T116	3865	83	0	0
T117	2356	8	0	0
T122	2560	11	0	0
T127	3317	19	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2744661	1173	0	0
T58	5910	9	0	0
T60	8901	4	0	0
T63	2483	38	0	0
T77	2538	5	0	0
T99	1764	5	0	0
T116	3865	61	0	0
T117	2356	49	0	0
T121	2768	22	0	0
T122	2560	1	0	0
T127	3317	8	0	0