Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	6620475	9490	0	0
StatusRise_A	6620475	13043	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6620475	9490	0	0
T1	4452	12	0	0
T2	6327	6	0	0
T3	8163	0	0	0
T4	44805	3	0	0
T5	11586	33	0	0
T6	5487	12	0	0
T7	8727	54	0	0
T8	46497	3	0	0
T9	2553	3	0	0
T10	6687	12	0	0
T16	0	15	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6620475	13043	0	0
T1	4452	15	0	0
T2	6327	9	0	0
T3	8163	15	0	0
T4	44805	6	0	0
T5	11586	36	0	0
T6	5487	15	0	0
T7	8727	60	0	0
T8	46497	6	0	0
T9	2553	9	0	0
T10	6687	15	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2206825	3197	0	0
StatusRise_A	2206825	4394	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2206825	3197	0	0
T1	1484	4	0	0
T2	2109	2	0	0
T3	2721	0	0	0
T4	14935	1	0	0
T5	3862	11	0	0
T6	1829	4	0	0
T7	2909	18	0	0
T8	15499	1	0	0
T9	851	1	0	0
T10	2229	4	0	0
T16	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2206825	4394	0	0
T1	1484	5	0	0
T2	2109	3	0	0
T3	2721	5	0	0
T4	14935	2	0	0
T5	3862	12	0	0
T6	1829	5	0	0
T7	2909	20	0	0
T8	15499	2	0	0
T9	851	3	0	0
T10	2229	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2206825	3197	0	0
StatusRise_A	2206825	4394	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2206825	3197	0	0
T1	1484	4	0	0
T2	2109	2	0	0
T3	2721	0	0	0
T4	14935	1	0	0
T5	3862	11	0	0
T6	1829	4	0	0
T7	2909	18	0	0
T8	15499	1	0	0
T9	851	1	0	0
T10	2229	4	0	0
T16	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2206825	4394	0	0
T1	1484	5	0	0
T2	2109	3	0	0
T3	2721	5	0	0
T4	14935	2	0	0
T5	3862	12	0	0
T6	1829	5	0	0
T7	2909	20	0	0
T8	15499	2	0	0
T9	851	3	0	0
T10	2229	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2206825	3096	0	0
StatusRise_A	2206825	4255	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2206825	3096	0	0
T1	1484	4	0	0
T2	2109	2	0	0
T3	2721	0	0	0
T4	14935	1	0	0
T5	3862	11	0	0
T6	1829	4	0	0
T7	2909	18	0	0
T8	15499	1	0	0
T9	851	1	0	0
T10	2229	4	0	0
T16	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2206825	4255	0	0
T1	1484	5	0	0
T2	2109	3	0	0
T3	2721	5	0	0
T4	14935	2	0	0
T5	3862	12	0	0
T6	1829	5	0	0
T7	2909	20	0	0
T8	15499	2	0	0
T9	851	3	0	0
T10	2229	5	0	0