Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	2207178	6211	0	0
EscTimeoutStoppedByClReset_A	2206825	77783	0	0
EscTimeoutTriggersReset_A	315021	298	0	0
RomAllowActiveState_A	2206825	4004	0	0
RomAllowCheckGoodState_A	2206825	4054	0	0
RomBlockActiveState_A	2206825	24765	0	0
RomBlockCheckGoodState_A	2206825	16550	0	0
RomIntgChkDisFalse_A	2206825	2020641	0	0
RomIntgChkDisTrue_A	2206825	26155	0	0
RstreqChkEsctimeout_A	2206825	1081	0	0
RstreqChkFsmterm_A	2206825	180	0	0
RstreqChkGlbesc_A	2206825	1081	0	0
RstreqChkMainpd_A	2206825	46244	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2207178	6211	0	0
T4	14936	54	0	0
T5	3863	0	0	0
T6	1829	0	0	0
T7	2910	0	0	0
T8	15500	259	0	0
T9	852	5	0	0
T10	2230	0	0	0
T16	1946	0	0	0
T17	1513	0	0	0
T46	4932	0	0	0
T48	0	4	0	0
T49	0	7	0	0
T91	0	271	0	0
T128	0	231	0	0
T129	0	40	0	0
T130	0	53	0	0
T131	0	117	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2206825	77783	0	0
T1	1484	70	0	0
T2	2109	30	0	0
T3	2721	48	0	0
T4	14935	9	0	0
T5	3862	564	0	0
T6	1829	59	0	0
T7	2909	365	0	0
T8	15499	52	0	0
T9	851	25	0	0
T10	2229	99	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315021	298	0	0
T4	657	3	0	0
T5	290	0	0	0
T6	341	0	0	0
T7	1030	0	0	0
T8	198	3	0	0
T9	272	3	0	0
T10	397	0	0	0
T16	524	0	0	0
T17	474	0	0	0
T46	373	0	0	0
T48	0	5	0	0
T49	0	6	0	0
T91	0	3	0	0
T128	0	3	0	0
T129	0	3	0	0
T132	0	4	0	0
T133	0	2	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2206825	4004	0	0
T1	1484	5	0	0
T2	2109	3	0	0
T3	2721	5	0	0
T4	14935	2	0	0
T5	3862	12	0	0
T6	1829	5	0	0
T7	2909	13	0	0
T8	15499	2	0	0
T9	851	3	0	0
T10	2229	5	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2206825	4054	0	0
T1	1484	5	0	0
T2	2109	3	0	0
T3	2721	5	0	0
T4	14935	2	0	0
T5	3862	12	0	0
T6	1829	5	0	0
T7	2909	14	0	0
T8	15499	2	0	0
T9	851	3	0	0
T10	2229	5	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2206825	24765	0	0
T16	1946	269	0	0
T17	1513	0	0	0
T27	0	353	0	0
T28	0	154	0	0
T29	0	297	0	0
T41	3343	0	0	0
T46	4931	0	0	0
T47	1724	0	0	0
T48	667	0	0	0
T49	788	0	0	0
T51	3129	0	0	0
T65	1953	0	0	0
T81	2781	0	0	0
T134	0	441	0	0
T135	0	1108	0	0
T136	0	90	0	0
T137	0	430	0	0
T138	0	207	0	0
T139	0	339	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2206825	16550	0	0
T16	1946	68	0	0
T17	1513	0	0	0
T27	0	142	0	0
T28	0	32	0	0
T29	0	933	0	0
T41	3343	0	0	0
T44	0	46	0	0
T46	4931	0	0	0
T47	1724	0	0	0
T48	667	0	0	0
T49	788	0	0	0
T51	3129	0	0	0
T65	1953	0	0	0
T81	2781	0	0	0
T134	0	288	0	0
T135	0	830	0	0
T136	0	9	0	0
T137	0	207	0	0
T138	0	115	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2206825	2020641	0	0
T1	1484	1124	0	0
T2	2109	2034	0	0
T3	2721	2336	0	0
T4	14935	14837	0	0
T5	3862	3803	0	0
T6	1829	1500	0	0
T7	2909	1979	0	0
T8	15499	15441	0	0
T9	851	669	0	0
T10	2229	1900	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2206825	26155	0	0
T16	1946	909	0	0
T17	1513	0	0	0
T27	0	967	0	0
T28	0	161	0	0
T29	0	575	0	0
T41	3343	0	0	0
T46	4931	0	0	0
T47	1724	0	0	0
T48	667	0	0	0
T49	788	0	0	0
T51	3129	0	0	0
T65	1953	0	0	0
T81	2781	0	0	0
T134	0	392	0	0
T135	0	2105	0	0
T136	0	262	0	0
T137	0	88	0	0
T138	0	442	0	0
T139	0	853	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2206825	1081	0	0
T4	14935	1	0	0
T5	3862	4	0	0
T6	1829	0	0	0
T7	2909	6	0	0
T8	15499	1	0	0
T9	851	1	0	0
T10	2229	0	0	0
T16	1946	2	0	0
T17	1513	0	0	0
T41	0	4	0	0
T46	4931	0	0	0
T47	0	3	0	0
T48	0	1	0	0
T49	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2206825	180	0	0
T19	14341	40	0	0
T20	0	20	0	0
T21	0	40	0	0
T30	0	40	0	0
T31	0	40	0	0
T32	2688	0	0	0
T33	2351	0	0	0
T34	7471	0	0	0
T35	2503	0	0	0
T36	2475	0	0	0
T37	1540	0	0	0
T38	7043	0	0	0
T39	3179	0	0	0
T40	5781	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2206825	1081	0	0
T4	14935	1	0	0
T5	3862	4	0	0
T6	1829	0	0	0
T7	2909	6	0	0
T8	15499	1	0	0
T9	851	1	0	0
T10	2229	0	0	0
T16	1946	2	0	0
T17	1513	0	0	0
T41	0	4	0	0
T46	4931	0	0	0
T47	0	3	0	0
T48	0	1	0	0
T49	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2206825	46244	0	0
T3	2721	20	0	0
T4	14935	0	0	0
T5	3862	499	0	0
T6	1829	0	0	0
T7	2909	121	0	0
T8	15499	0	0	0
T9	851	0	0	0
T10	2229	0	0	0
T16	1946	77	0	0
T17	0	23	0	0
T18	0	22	0	0
T41	0	137	0	0
T42	0	190	0	0
T43	0	656	0	0
T46	4931	0	0	0
T90	0	6	0	0