Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T16
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T29,T55

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	2202104	138	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	2202104	11795	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	2202104	151126	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	2202104	11795	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	2202104	138	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	2202104	11795	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	2202104	151126	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	2202104	11795	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2202104	138	0	0
T11	1412	0	0	0
T12	2182	0	0	0
T13	1411	1	0	0
T14	3566	0	0	0
T16	2900	2	0	0
T18	1570	0	0	0
T29	1472	3	0	0
T42	1606	0	0	0
T48	1459	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T55	0	3	0	0
T62	2022	0	0	0
T64	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2202104	11795	0	0
T11	1412	0	0	0
T12	2182	0	0	0
T13	1411	10	0	0
T14	3566	0	0	0
T16	2900	420	0	0
T18	1570	0	0	0
T29	1472	294	0	0
T42	1606	0	0	0
T48	1459	0	0	0
T51	0	11	0	0
T52	0	13	0	0
T55	0	223	0	0
T62	2022	0	0	0
T64	0	11	0	0
T78	0	11	0	0
T79	0	12	0	0
T80	0	13	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2202104	151126	0	0
T10	1220	805	0	0
T11	1412	0	0	0
T12	2182	0	0	0
T13	1411	1113	0	0
T14	3566	2768	0	0
T15	0	1157	0	0
T16	2900	738	0	0
T17	0	1112	0	0
T18	1570	0	0	0
T29	1472	717	0	0
T41	7989	0	0	0
T48	1459	0	0	0
T51	0	929	0	0
T52	0	804	0	0
T78	0	1016	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2202104	11795	0	0
T11	1412	0	0	0
T12	2182	0	0	0
T13	1411	10	0	0
T14	3566	0	0	0
T16	2900	420	0	0
T18	1570	0	0	0
T29	1472	294	0	0
T42	1606	0	0	0
T48	1459	0	0	0
T51	0	11	0	0
T52	0	13	0	0
T55	0	223	0	0
T62	2022	0	0	0
T64	0	11	0	0
T78	0	11	0	0
T79	0	12	0	0
T80	0	13	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2202104	138	0	0
T11	1412	0	0	0
T12	2182	0	0	0
T13	1411	1	0	0
T14	3566	0	0	0
T16	2900	2	0	0
T18	1570	0	0	0
T29	1472	3	0	0
T42	1606	0	0	0
T48	1459	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T55	0	3	0	0
T62	2022	0	0	0
T64	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2202104	11795	0	0
T11	1412	0	0	0
T12	2182	0	0	0
T13	1411	10	0	0
T14	3566	0	0	0
T16	2900	420	0	0
T18	1570	0	0	0
T29	1472	294	0	0
T42	1606	0	0	0
T48	1459	0	0	0
T51	0	11	0	0
T52	0	13	0	0
T55	0	223	0	0
T62	2022	0	0	0
T64	0	11	0	0
T78	0	11	0	0
T79	0	12	0	0
T80	0	13	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2202104	151126	0	0
T10	1220	805	0	0
T11	1412	0	0	0
T12	2182	0	0	0
T13	1411	1113	0	0
T14	3566	2768	0	0
T15	0	1157	0	0
T16	2900	738	0	0
T17	0	1112	0	0
T18	1570	0	0	0
T29	1472	717	0	0
T41	7989	0	0	0
T48	1459	0	0	0
T51	0	929	0	0
T52	0	804	0	0
T78	0	1016	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2202104	11795	0	0
T11	1412	0	0	0
T12	2182	0	0	0
T13	1411	10	0	0
T14	3566	0	0	0
T16	2900	420	0	0
T18	1570	0	0	0
T29	1472	294	0	0
T42	1606	0	0	0
T48	1459	0	0	0
T51	0	11	0	0
T52	0	13	0	0
T55	0	223	0	0
T62	2022	0	0	0
T64	0	11	0	0
T78	0	11	0	0
T79	0	12	0	0
T80	0	13	0	0