Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2773750	13172	0	0
intr_enable_rd_A	2773750	3875	0	0
reset_en_rd_A	2773750	1609	0	0
reset_en_regwen_rd_A	2773750	1359	0	0
wake_info_capture_dis_rd_A	2773750	1266	0	0
wakeup_en_rd_A	2773750	2256	0	0
wakeup_en_regwen_rd_A	2773750	1323	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2773750	13172	0	0
T24	2239	55	0	0
T25	1626	212	0	0
T26	3922	6	0	0
T56	13038	1270	0	0
T57	3715	811	0	0
T58	1783	52	0	0
T59	7809	7	0	0
T69	4786	392	0	0
T73	2872	32	0	0
T74	1238	14	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2773750	3875	0	0
T27	2170	0	0	0
T46	3274	0	0	0
T53	0	33	0	0
T55	1505	0	0	0
T63	5726	44	0	0
T64	1017	0	0	0
T76	4275	55	0	0
T79	1191	5	0	0
T80	1303	4	0	0
T82	0	30	0	0
T83	0	6	0	0
T113	0	39	0	0
T114	0	18	0	0
T115	0	8	0	0
T116	2378	0	0	0
T117	1507	0	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2773750	1609	0	0
T24	2239	4	0	0
T60	9356	57	0	0
T65	3014	24	0	0
T71	2172	18	0	0
T84	3503	3	0	0
T92	1293	7	0	0
T106	4174	85	0	0
T118	9229	137	0	0
T119	2835	30	0	0
T120	5710	52	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2773750	1359	0	0
T24	2239	4	0	0
T60	9356	59	0	0
T65	3014	11	0	0
T70	1370	1	0	0
T71	2172	28	0	0
T92	1293	13	0	0
T94	1460	5	0	0
T106	4174	61	0	0
T118	9229	66	0	0
T119	2835	31	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2773750	1266	0	0
T24	2239	8	0	0
T60	9356	36	0	0
T65	3014	7	0	0
T71	2172	19	0	0
T84	3503	6	0	0
T92	1293	3	0	0
T94	1460	1	0	0
T106	4174	58	0	0
T118	9229	71	0	0
T119	2835	17	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2773750	2256	0	0
T24	2239	8	0	0
T60	9356	170	0	0
T65	3014	30	0	0
T70	1370	4	0	0
T71	2172	9	0	0
T84	3503	6	0	0
T92	1293	49	0	0
T94	1460	2	0	0
T106	4174	65	0	0
T118	9229	192	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2773750	1323	0	0
T24	2239	8	0	0
T60	9356	42	0	0
T65	3014	8	0	0
T70	1370	9	0	0
T71	2172	37	0	0
T84	3503	9	0	0
T92	1293	5	0	0
T94	1460	10	0	0
T106	4174	18	0	0
T118	9229	50	0	0