Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	6606312	9205	0	0
StatusRise_A	6606312	12518	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6606312	9205	0	0
T1	20727	54	0	0
T2	7149	15	0	0
T3	17541	24	0	0
T4	3846	0	0	0
T5	4077	3	0	0
T6	2910	0	0	0
T7	7809	21	0	0
T8	2955	0	0	0
T9	8637	15	0	0
T10	3660	19	0	0
T13	0	6	0	0
T16	0	12	0	0
T41	0	54	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6606312	12518	0	0
T1	20727	57	0	0
T2	7149	18	0	0
T3	17541	30	0	0
T4	3846	12	0	0
T5	4077	9	0	0
T6	2910	18	0	0
T7	7809	24	0	0
T8	2955	6	0	0
T9	8637	21	0	0
T10	3660	21	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2202104	3109	0	0
StatusRise_A	2202104	4223	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2202104	3109	0	0
T1	6909	18	0	0
T2	2383	5	0	0
T3	5847	8	0	0
T4	1282	0	0	0
T5	1359	1	0	0
T6	970	0	0	0
T7	2603	7	0	0
T8	985	0	0	0
T9	2879	5	0	0
T10	1220	7	0	0
T13	0	2	0	0
T16	0	4	0	0
T41	0	18	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2202104	4223	0	0
T1	6909	19	0	0
T2	2383	6	0	0
T3	5847	10	0	0
T4	1282	4	0	0
T5	1359	3	0	0
T6	970	6	0	0
T7	2603	8	0	0
T8	985	2	0	0
T9	2879	7	0	0
T10	1220	8	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2202104	3109	0	0
StatusRise_A	2202104	4223	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2202104	3109	0	0
T1	6909	18	0	0
T2	2383	5	0	0
T3	5847	8	0	0
T4	1282	0	0	0
T5	1359	1	0	0
T6	970	0	0	0
T7	2603	7	0	0
T8	985	0	0	0
T9	2879	5	0	0
T10	1220	7	0	0
T13	0	2	0	0
T16	0	4	0	0
T41	0	18	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2202104	4223	0	0
T1	6909	19	0	0
T2	2383	6	0	0
T3	5847	10	0	0
T4	1282	4	0	0
T5	1359	3	0	0
T6	970	6	0	0
T7	2603	8	0	0
T8	985	2	0	0
T9	2879	7	0	0
T10	1220	8	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2202104	2987	0	0
StatusRise_A	2202104	4072	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2202104	2987	0	0
T1	6909	18	0	0
T2	2383	5	0	0
T3	5847	8	0	0
T4	1282	0	0	0
T5	1359	1	0	0
T6	970	0	0	0
T7	2603	7	0	0
T8	985	0	0	0
T9	2879	5	0	0
T10	1220	5	0	0
T13	0	2	0	0
T16	0	4	0	0
T41	0	18	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2202104	4072	0	0
T1	6909	19	0	0
T2	2383	6	0	0
T3	5847	10	0	0
T4	1282	4	0	0
T5	1359	3	0	0
T6	970	6	0	0
T7	2603	8	0	0
T8	985	2	0	0
T9	2879	7	0	0
T10	1220	5	0	0