Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	2202463	5681	0	0
EscTimeoutStoppedByClReset_A	2202104	73560	0	0
EscTimeoutTriggersReset_A	311812	311	0	0
RomAllowActiveState_A	2202104	3848	0	0
RomAllowCheckGoodState_A	2202104	3903	0	0
RomBlockActiveState_A	2202104	33130	0	0
RomBlockCheckGoodState_A	2202104	21372	0	0
RomIntgChkDisFalse_A	2202104	2018501	0	0
RomIntgChkDisTrue_A	2202104	34575	0	0
RstreqChkEsctimeout_A	2202104	925	0	0
RstreqChkFsmterm_A	2202104	120	0	0
RstreqChkGlbesc_A	2202104	925	0	0
RstreqChkMainpd_A	2202104	57996	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2202463	5681	0	0
T11	1413	16	0	0
T12	2183	0	0	0
T14	3566	0	0	0
T18	1571	0	0	0
T34	0	29	0	0
T35	0	16	0	0
T42	1607	0	0	0
T43	3167	0	0	0
T47	15113	141	0	0
T51	1422	0	0	0
T62	2023	0	0	0
T121	0	21	0	0
T122	0	65	0	0
T123	0	31	0	0
T124	0	242	0	0
T125	0	4	0	0
T126	0	35	0	0
T127	2979	0	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2202104	73560	0	0
T1	6909	319	0	0
T2	2383	205	0	0
T3	5847	379	0	0
T4	1282	5	0	0
T5	1359	51	0	0
T6	970	28	0	0
T7	2603	238	0	0
T8	985	5	0	0
T9	2879	138	0	0
T10	1220	0	0	0
T41	0	283	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311812	311	0	0
T5	221	4	0	0
T6	775	0	0	0
T7	396	0	0	0
T8	1414	0	0	0
T9	449	0	0	0
T10	336	0	0	0
T11	0	4	0	0
T12	0	3	0	0
T13	450	0	0	0
T16	289	0	0	0
T41	760	0	0	0
T47	0	3	0	0
T48	856	0	0	0
T116	0	3	0	0
T121	0	3	0	0
T122	0	2	0	0
T128	0	5	0	0
T129	0	5	0	0
T130	0	3	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2202104	3848	0	0
T1	6909	12	0	0
T2	2383	6	0	0
T3	5847	10	0	0
T4	1282	4	0	0
T5	1359	3	0	0
T6	970	6	0	0
T7	2603	8	0	0
T8	985	2	0	0
T9	2879	7	0	0
T10	1220	8	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2202104	3903	0	0
T1	6909	13	0	0
T2	2383	6	0	0
T3	5847	10	0	0
T4	1282	4	0	0
T5	1359	3	0	0
T6	970	6	0	0
T7	2603	8	0	0
T8	985	2	0	0
T9	2879	7	0	0
T10	1220	8	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2202104	33130	0	0
T3	5847	1218	0	0
T4	1282	0	0	0
T5	1359	0	0	0
T6	970	0	0	0
T7	2603	444	0	0
T8	985	0	0	0
T9	2879	538	0	0
T10	1220	0	0	0
T13	1411	0	0	0
T41	7989	0	0	0
T131	0	127	0	0
T132	0	198	0	0
T133	0	195	0	0
T134	0	1100	0	0
T135	0	385	0	0
T136	0	994	0	0
T137	0	294	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2202104	21372	0	0
T3	5847	1054	0	0
T4	1282	0	0	0
T5	1359	0	0	0
T6	970	0	0	0
T7	2603	242	0	0
T8	985	0	0	0
T9	2879	280	0	0
T10	1220	0	0	0
T13	1411	0	0	0
T41	7989	0	0	0
T132	0	175	0	0
T133	0	19	0	0
T134	0	748	0	0
T135	0	191	0	0
T136	0	666	0	0
T137	0	40	0	0
T138	0	102	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2202104	2018501	0	0
T1	6909	6039	0	0
T2	2383	2286	0	0
T3	5847	5447	0	0
T4	1282	950	0	0
T5	1359	1224	0	0
T6	970	483	0	0
T7	2603	1332	0	0
T8	985	859	0	0
T9	2879	2592	0	0
T10	1220	1159	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2202104	34575	0	0
T3	5847	275	0	0
T4	1282	0	0	0
T5	1359	0	0	0
T6	970	0	0	0
T7	2603	1195	0	0
T8	985	0	0	0
T9	2879	125	0	0
T10	1220	0	0	0
T13	1411	0	0	0
T41	7989	0	0	0
T131	0	345	0	0
T132	0	62	0	0
T133	0	892	0	0
T134	0	1564	0	0
T135	0	47	0	0
T136	0	698	0	0
T137	0	890	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2202104	925	0	0
T1	6909	8	0	0
T2	2383	2	0	0
T3	5847	2	0	0
T4	1282	3	0	0
T5	1359	1	0	0
T6	970	0	0	0
T7	2603	1	0	0
T8	985	1	0	0
T9	2879	4	0	0
T10	1220	0	0	0
T41	0	4	0	0
T48	0	3	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2202104	120	0	0
T21	9014	20	0	0
T22	0	20	0	0
T23	0	20	0	0
T30	0	40	0	0
T31	0	20	0	0
T32	1435	0	0	0
T33	4148	0	0	0
T34	14900	0	0	0
T35	14800	0	0	0
T36	2999	0	0	0
T37	3186	0	0	0
T38	2539	0	0	0
T39	4703	0	0	0
T40	2244	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2202104	925	0	0
T1	6909	8	0	0
T2	2383	2	0	0
T3	5847	2	0	0
T4	1282	3	0	0
T5	1359	1	0	0
T6	970	0	0	0
T7	2603	1	0	0
T8	985	1	0	0
T9	2879	4	0	0
T10	1220	0	0	0
T41	0	4	0	0
T48	0	3	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2202104	57996	0	0
T1	6909	141	0	0
T2	2383	180	0	0
T3	5847	1918	0	0
T4	1282	0	0	0
T5	1359	0	0	0
T6	970	22	0	0
T7	2603	494	0	0
T8	985	0	0	0
T9	2879	84	0	0
T10	1220	0	0	0
T18	0	27	0	0
T41	0	138	0	0
T42	0	78	0	0
T43	0	560	0	0