Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	37718	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

28381

1

T1

15

T2

11

T3

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	33828	1			T1	16		T2	13		T3	43
values[0x0]	15904	1			T1	16		T2	4		T3	29
values[0x1]	16367	1			T1	17		T2	7		T3	34

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	30084	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

36015

1

T1

18

T2

15

T3

41

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	261	1			T7	4		T52	1		T41	2
valid_sources[0x01]	208	1			T3	1		T28	1		T89	2
valid_sources[0x02]	345	1			T4	3		T89	1		T14	1
valid_sources[0x03]	212	1			T5	2		T89	2		T13	1
valid_sources[0x04]	414	1			T4	1		T5	3		T203	1
valid_sources[0x05]	223	1			T6	1		T28	1		T26	1
valid_sources[0x06]	295	1			T3	1		T90	2		T41	2
valid_sources[0x07]	227	1			T5	1		T15	1		T26	1
valid_sources[0x08]	335	1			T89	4		T204	5		T60	14
valid_sources[0x09]	253	1			T5	4		T205	1		T203	1
valid_sources[0x0a]	200	1			T3	1		T5	1		T89	8
valid_sources[0x0b]	163	1			T28	1		T13	1		T204	3
valid_sources[0x0c]	357	1			T5	2		T206	2		T207	2
valid_sources[0x0d]	245	1			T14	1		T205	1		T203	1
valid_sources[0x0e]	245	1			T1	1		T3	1		T47	2
valid_sources[0x0f]	244	1			T5	3		T28	1		T41	5
valid_sources[0x10]	221	1			T3	1		T5	1		T89	3
valid_sources[0x11]	293	1			T5	1		T28	1		T90	3
valid_sources[0x12]	189	1			T3	2		T89	2		T13	1
valid_sources[0x13]	363	1			T1	1		T3	1		T26	1
valid_sources[0x14]	284	1			T3	4		T5	4		T15	1
valid_sources[0x15]	489	1			T5	1		T6	1		T52	1
valid_sources[0x16]	208	1			T2	1		T13	3		T94	2
valid_sources[0x17]	351	1			T41	2		T89	1		T13	1
valid_sources[0x18]	323	1			T4	1		T89	3		T14	3
valid_sources[0x19]	242	1			T3	1		T6	1		T28	2
valid_sources[0x1a]	252	1			T5	4		T15	1		T28	1
valid_sources[0x1b]	209	1			T5	3		T89	1		T13	2
valid_sources[0x1c]	313	1			T2	2		T52	1		T92	2
valid_sources[0x1d]	158	1			T15	1		T28	1		T89	1
valid_sources[0x1e]	228	1			T13	2		T204	1		T14	1
valid_sources[0x1f]	178	1			T5	4		T6	1		T89	2
valid_sources[0x20]	172	1			T89	6		T204	4		T43	1
valid_sources[0x21]	251	1			T5	1		T13	4		T205	1
valid_sources[0x22]	274	1			T3	1		T5	2		T47	1
valid_sources[0x23]	204	1			T3	1		T41	2		T89	1
valid_sources[0x24]	339	1			T89	3		T206	1		T208	2
valid_sources[0x25]	231	1			T3	1		T5	2		T10	1
valid_sources[0x26]	247	1			T5	1		T204	1		T206	1
valid_sources[0x27]	264	1			T208	3		T209	2		T144	1
valid_sources[0x28]	218	1			T203	1		T60	13		T206	1
valid_sources[0x29]	257	1			T26	2		T13	2		T92	2
valid_sources[0x2a]	252	1			T3	1		T5	1		T52	1
valid_sources[0x2b]	196	1			T89	1		T13	2		T204	1
valid_sources[0x2c]	566	1			T7	4		T13	1		T43	1
valid_sources[0x2d]	222	1			T3	2		T89	2		T13	1
valid_sources[0x2e]	247	1			T41	1		T203	2		T138	2
valid_sources[0x2f]	247	1			T3	2		T47	1		T41	4
valid_sources[0x30]	249	1			T3	1		T5	4		T52	1
valid_sources[0x31]	228	1			T3	1		T41	2		T89	7
valid_sources[0x32]	235	1			T13	1		T14	1		T208	2
valid_sources[0x33]	219	1			T6	1		T28	1		T89	1
valid_sources[0x34]	158	1			T52	2		T89	1		T203	1
valid_sources[0x35]	191	1			T28	2		T89	1		T13	4
valid_sources[0x36]	309	1			T1	3		T5	17		T89	1
valid_sources[0x37]	249	1			T28	2		T41	1		T206	2
valid_sources[0x38]	333	1			T1	2		T5	4		T42	58
valid_sources[0x39]	309	1			T6	1		T7	1		T26	1
valid_sources[0x3a]	221	1			T50	1		T13	1		T14	8
valid_sources[0x3b]	254	1			T1	2		T89	2		T13	3
valid_sources[0x3c]	264	1			T5	5		T26	2		T41	1
valid_sources[0x3d]	207	1			T3	1		T204	1		T99	1
valid_sources[0x3e]	255	1			T28	2		T90	2		T13	1
valid_sources[0x3f]	207	1			T3	1		T89	5		T204	4
valid_sources[0x40]	222	1			T3	1		T204	7		T203	5
valid_sources[0x41]	237	1			T3	3		T51	26		T43	1
valid_sources[0x42]	309	1			T2	5		T5	1		T41	1
valid_sources[0x43]	235	1			T5	3		T14	1		T60	14
valid_sources[0x44]	173	1			T3	2		T13	2		T203	2
valid_sources[0x45]	314	1			T3	2		T5	9		T204	2
valid_sources[0x46]	285	1			T3	1		T5	1		T28	1
valid_sources[0x47]	334	1			T91	28		T89	1		T13	2
valid_sources[0x48]	226	1			T3	1		T89	1		T43	1
valid_sources[0x49]	278	1			T3	2		T5	3		T15	1
valid_sources[0x4a]	237	1			T4	4		T203	1		T210	2
valid_sources[0x4b]	251	1			T5	10		T52	1		T89	3
valid_sources[0x4c]	201	1			T5	1		T47	1		T89	1
valid_sources[0x4d]	330	1			T26	2		T13	4		T92	1
valid_sources[0x4e]	190	1			T15	1		T13	2		T14	1
valid_sources[0x4f]	324	1			T3	2		T5	3		T7	3
valid_sources[0x50]	209	1			T47	1		T89	1		T204	3
valid_sources[0x51]	276	1			T2	4		T15	1		T41	1
valid_sources[0x52]	253	1			T28	2		T89	1		T138	1
valid_sources[0x53]	216	1			T28	1		T203	1		T94	1
valid_sources[0x54]	397	1			T3	1		T204	2		T205	1
valid_sources[0x55]	223	1			T53	20		T13	1		T204	1
valid_sources[0x56]	190	1			T3	1		T41	1		T89	1
valid_sources[0x57]	217	1			T5	11		T15	1		T94	1
valid_sources[0x58]	181	1			T6	1		T27	3		T89	3
valid_sources[0x59]	236	1			T204	5		T43	2		T205	1
valid_sources[0x5a]	255	1			T5	7		T89	10		T204	3
valid_sources[0x5b]	236	1			T5	1		T41	1		T43	1
valid_sources[0x5c]	272	1			T7	1		T26	2		T41	4
valid_sources[0x5d]	301	1			T2	1		T5	1		T6	1
valid_sources[0x5e]	242	1			T5	8		T93	1		T208	1
valid_sources[0x5f]	179	1			T89	1		T13	1		T99	3
valid_sources[0x60]	211	1			T41	1		T43	1		T93	2
valid_sources[0x61]	188	1			T28	1		T89	3		T43	2
valid_sources[0x62]	210	1			T15	1		T90	1		T27	6
valid_sources[0x63]	260	1			T26	2		T27	1		T92	8
valid_sources[0x64]	348	1			T3	2		T5	6		T15	2
valid_sources[0x65]	340	1			T6	1		T206	2		T207	2
valid_sources[0x66]	198	1			T41	2		T89	2		T204	4
valid_sources[0x67]	200	1			T3	2		T4	5		T26	1
valid_sources[0x68]	160	1			T5	4		T204	4		T14	2
valid_sources[0x69]	194	1			T6	1		T52	1		T15	1
valid_sources[0x6a]	203	1			T1	2		T3	1		T5	1
valid_sources[0x6b]	390	1			T1	2		T5	1		T90	4
valid_sources[0x6c]	299	1			T13	1		T204	1		T60	11
valid_sources[0x6d]	211	1			T1	2		T5	5		T13	6
valid_sources[0x6e]	222	1			T52	1		T89	2		T13	1
valid_sources[0x6f]	252	1			T5	4		T89	1		T204	3
valid_sources[0x70]	227	1			T28	1		T41	2		T13	1
valid_sources[0x71]	331	1			T13	2		T43	1		T211	1
valid_sources[0x72]	222	1			T1	3		T3	1		T5	2
valid_sources[0x73]	219	1			T3	2		T89	2		T13	1
valid_sources[0x74]	219	1			T2	1		T203	1		T94	1
valid_sources[0x75]	458	1			T1	5		T3	1		T5	5
valid_sources[0x76]	187	1			T89	1		T204	1		T92	1
valid_sources[0x77]	261	1			T3	3		T5	2		T128	1
valid_sources[0x78]	216	1			T5	4		T6	1		T203	1
valid_sources[0x79]	163	1			T4	2		T13	4		T43	1
valid_sources[0x7a]	246	1			T1	1		T5	1		T89	1
valid_sources[0x7b]	491	1			T15	1		T41	1		T204	1
valid_sources[0x7c]	227	1			T1	1		T5	3		T205	1
valid_sources[0x7d]	314	1			T28	1		T90	2		T204	1
valid_sources[0x7e]	193	1			T41	1		T89	2		T203	2
valid_sources[0x7f]	261	1			T3	1		T15	2		T24	1
valid_sources[0x80]	298	1			T5	7		T6	1		T13	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14021

1

T1

6

T2

8

T3

3

values[0x0]

all_enables

biggest_size

8179

1

T1

5

T2

1

T3

15

values[0x1]

all_enables

biggest_size

6181

1

T1

4

T2

2

T3

3