Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T52,T53

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	2182366	147	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	2182366	11882	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	2182366	142875	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	2182366	11882	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	2182366	147	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	2182366	11882	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	2182366	142875	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	2182366	11882	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2182366	147	0	0
T2	1267	1	0	0
T3	1530	0	0	0
T4	1397	1	0	0
T5	2798	0	0	0
T6	1024	1	0	0
T7	1336	2	0	0
T8	2521	0	0	0
T9	1478	0	0	0
T10	2572	0	0	0
T50	0	4	0	0
T52	1626	3	0	0
T53	0	2	0	0
T90	0	3	0	0
T91	0	1	0	0
T92	0	2	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2182366	11882	0	0
T2	1267	12	0	0
T3	1530	0	0	0
T4	1397	10	0	0
T5	2798	0	0	0
T6	1024	13	0	0
T7	1336	140	0	0
T8	2521	0	0	0
T9	1478	0	0	0
T10	2572	0	0	0
T50	0	360	0	0
T52	1626	271	0	0
T53	0	168	0	0
T90	0	803	0	0
T91	0	12	0	0
T92	0	247	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2182366	142875	0	0
T2	1267	957	0	0
T3	1530	0	0	0
T4	1397	1100	0	0
T5	2798	1306	0	0
T6	1024	839	0	0
T7	1336	680	0	0
T8	2521	0	0	0
T9	1478	0	0	0
T10	2572	0	0	0
T50	0	813	0	0
T52	1626	842	0	0
T53	0	896	0	0
T90	0	408	0	0
T91	0	1627	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2182366	11882	0	0
T2	1267	12	0	0
T3	1530	0	0	0
T4	1397	10	0	0
T5	2798	0	0	0
T6	1024	13	0	0
T7	1336	140	0	0
T8	2521	0	0	0
T9	1478	0	0	0
T10	2572	0	0	0
T50	0	360	0	0
T52	1626	271	0	0
T53	0	168	0	0
T90	0	803	0	0
T91	0	12	0	0
T92	0	247	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2182366	147	0	0
T2	1267	1	0	0
T3	1530	0	0	0
T4	1397	1	0	0
T5	2798	0	0	0
T6	1024	1	0	0
T7	1336	2	0	0
T8	2521	0	0	0
T9	1478	0	0	0
T10	2572	0	0	0
T50	0	4	0	0
T52	1626	3	0	0
T53	0	2	0	0
T90	0	3	0	0
T91	0	1	0	0
T92	0	2	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2182366	11882	0	0
T2	1267	12	0	0
T3	1530	0	0	0
T4	1397	10	0	0
T5	2798	0	0	0
T6	1024	13	0	0
T7	1336	140	0	0
T8	2521	0	0	0
T9	1478	0	0	0
T10	2572	0	0	0
T50	0	360	0	0
T52	1626	271	0	0
T53	0	168	0	0
T90	0	803	0	0
T91	0	12	0	0
T92	0	247	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2182366	142875	0	0
T2	1267	957	0	0
T3	1530	0	0	0
T4	1397	1100	0	0
T5	2798	1306	0	0
T6	1024	839	0	0
T7	1336	680	0	0
T8	2521	0	0	0
T9	1478	0	0	0
T10	2572	0	0	0
T50	0	813	0	0
T52	1626	842	0	0
T53	0	896	0	0
T90	0	408	0	0
T91	0	1627	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2182366	11882	0	0
T2	1267	12	0	0
T3	1530	0	0	0
T4	1397	10	0	0
T5	2798	0	0	0
T6	1024	13	0	0
T7	1336	140	0	0
T8	2521	0	0	0
T9	1478	0	0	0
T10	2572	0	0	0
T50	0	360	0	0
T52	1626	271	0	0
T53	0	168	0	0
T90	0	803	0	0
T91	0	12	0	0
T92	0	247	0	0