Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2755588	12555	0	0
intr_enable_rd_A	2755588	2505	0	0
reset_en_rd_A	2755588	1507	0	0
reset_en_regwen_rd_A	2755588	1306	0	0
wake_info_capture_dis_rd_A	2755588	1352	0	0
wakeup_en_rd_A	2755588	2280	0	0
wakeup_en_regwen_rd_A	2755588	1295	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2755588	12555	0	0
T21	3092	101	0	0
T22	1259	11	0	0
T23	7975	461	0	0
T61	7873	4	0	0
T62	9753	8	0	0
T63	7740	12	0	0
T64	4020	116	0	0
T65	1924	16	0	0
T70	15452	9	0	0
T84	3449	63	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2755588	2505	0	0
T14	0	33	0	0
T27	4885	0	0	0
T38	0	19	0	0
T41	5958	0	0	0
T47	777	0	0	0
T48	1198	0	0	0
T88	2199	0	0	0
T89	7184	95	0	0
T91	2532	4	0	0
T102	0	60	0	0
T103	0	21	0	0
T123	0	87	0	0
T124	0	54	0	0
T125	0	3	0	0
T126	0	100	0	0
T127	15603	0	0	0
T128	1049	0	0	0
T129	583	0	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2755588	1507	0	0
T23	7975	17	0	0
T62	9753	21	0	0
T66	4681	12	0	0
T72	4807	38	0	0
T82	5262	41	0	0
T87	9957	72	0	0
T106	1189	18	0	0
T121	4196	16	0	0
T122	3097	2	0	0
T130	1198	13	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2755588	1306	0	0
T23	7975	33	0	0
T62	9753	14	0	0
T66	4681	7	0	0
T82	5262	16	0	0
T87	9957	41	0	0
T106	1189	5	0	0
T121	4196	35	0	0
T122	3097	29	0	0
T130	1198	11	0	0
T131	1865	2	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2755588	1352	0	0
T23	7975	22	0	0
T62	9753	14	0	0
T66	4681	6	0	0
T82	5262	47	0	0
T87	9957	33	0	0
T106	1189	10	0	0
T121	4196	29	0	0
T122	3097	49	0	0
T130	1198	4	0	0
T131	1865	5	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2755588	2280	0	0
T23	7975	8	0	0
T62	9753	105	0	0
T72	4807	111	0	0
T82	5262	114	0	0
T87	9957	134	0	0
T106	1189	23	0	0
T121	4196	25	0	0
T122	3097	3	0	0
T130	1198	15	0	0
T132	3836	31	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2755588	1295	0	0
T23	7975	22	0	0
T62	9753	38	0	0
T72	4807	38	0	0
T82	5262	30	0	0
T87	9957	50	0	0
T106	1189	7	0	0
T121	4196	42	0	0
T122	3097	24	0	0
T130	1198	8	0	0
T132	3836	18	0	0