Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	6547098	9216	0	0
StatusRise_A	6547098	12630	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6547098	9216	0	0
T1	7182	54	0	0
T2	3801	6	0	0
T3	4590	12	0	0
T4	4191	6	0	0
T5	8394	38	0	0
T6	3072	6	0	0
T7	4008	12	0	0
T8	7563	3	0	0
T9	4434	0	0	0
T10	7716	0	0	0
T15	0	18	0	0
T52	0	12	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6547098	12630	0	0
T1	7182	60	0	0
T2	3801	9	0	0
T3	4590	15	0	0
T4	4191	9	0	0
T5	8394	41	0	0
T6	3072	9	0	0
T7	4008	15	0	0
T8	7563	9	0	0
T9	4434	18	0	0
T10	7716	15	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2182366	3102	0	0
StatusRise_A	2182366	4254	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2182366	3102	0	0
T1	2394	18	0	0
T2	1267	2	0	0
T3	1530	4	0	0
T4	1397	2	0	0
T5	2798	13	0	0
T6	1024	2	0	0
T7	1336	4	0	0
T8	2521	1	0	0
T9	1478	0	0	0
T10	2572	0	0	0
T15	0	6	0	0
T52	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2182366	4254	0	0
T1	2394	20	0	0
T2	1267	3	0	0
T3	1530	5	0	0
T4	1397	3	0	0
T5	2798	14	0	0
T6	1024	3	0	0
T7	1336	5	0	0
T8	2521	3	0	0
T9	1478	6	0	0
T10	2572	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2182366	3102	0	0
StatusRise_A	2182366	4254	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2182366	3102	0	0
T1	2394	18	0	0
T2	1267	2	0	0
T3	1530	4	0	0
T4	1397	2	0	0
T5	2798	13	0	0
T6	1024	2	0	0
T7	1336	4	0	0
T8	2521	1	0	0
T9	1478	0	0	0
T10	2572	0	0	0
T15	0	6	0	0
T52	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2182366	4254	0	0
T1	2394	20	0	0
T2	1267	3	0	0
T3	1530	5	0	0
T4	1397	3	0	0
T5	2798	14	0	0
T6	1024	3	0	0
T7	1336	5	0	0
T8	2521	3	0	0
T9	1478	6	0	0
T10	2572	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2182366	3012	0	0
StatusRise_A	2182366	4122	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2182366	3012	0	0
T1	2394	18	0	0
T2	1267	2	0	0
T3	1530	4	0	0
T4	1397	2	0	0
T5	2798	12	0	0
T6	1024	2	0	0
T7	1336	4	0	0
T8	2521	1	0	0
T9	1478	0	0	0
T10	2572	0	0	0
T15	0	6	0	0
T52	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2182366	4122	0	0
T1	2394	20	0	0
T2	1267	3	0	0
T3	1530	5	0	0
T4	1397	3	0	0
T5	2798	13	0	0
T6	1024	3	0	0
T7	1336	5	0	0
T8	2521	3	0	0
T9	1478	6	0	0
T10	2572	5	0	0