Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	2182725	6259	0	0
EscTimeoutStoppedByClReset_A	2182366	73035	0	0
EscTimeoutTriggersReset_A	318124	328	0	0
RomAllowActiveState_A	2182366	3864	0	0
RomAllowCheckGoodState_A	2182366	3914	0	0
RomBlockActiveState_A	2182366	26926	0	0
RomBlockCheckGoodState_A	2182366	16465	0	0
RomIntgChkDisFalse_A	2182366	1999327	0	0
RomIntgChkDisTrue_A	2182366	29442	0	0
RstreqChkEsctimeout_A	2182366	994	0	0
RstreqChkFsmterm_A	2182366	140	0	0
RstreqChkGlbesc_A	2182366	994	0	0
RstreqChkMainpd_A	2182366	46536	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2182725	6259	0	0
T8	2521	22	0	0
T9	1479	0	0	0
T10	2572	0	0	0
T11	847	0	0	0
T12	0	271	0	0
T15	2105	0	0	0
T28	2952	0	0	0
T45	0	258	0	0
T46	0	277	0	0
T49	3292	0	0	0
T50	1343	0	0	0
T52	1626	0	0	0
T53	1629	0	0	0
T127	0	278	0	0
T129	0	1	0	0
T133	0	3	0	0
T134	0	10	0	0
T135	0	41	0	0
T136	0	175	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2182366	73035	0	0
T1	2394	250	0	0
T2	1267	12	0	0
T3	1530	48	0	0
T4	1397	10	0	0
T5	2798	0	0	0
T6	1024	13	0	0
T7	1336	45	0	0
T8	2521	11	0	0
T9	1478	19	0	0
T10	2572	13	0	0
T52	0	31	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	318124	328	0	0
T8	216	2	0	0
T9	787	0	0	0
T10	274	0	0	0
T11	267	5	0	0
T12	0	3	0	0
T15	628	0	0	0
T28	1298	0	0	0
T45	0	3	0	0
T46	0	3	0	0
T49	329	0	0	0
T50	1423	0	0	0
T52	572	0	0	0
T53	952	0	0	0
T127	0	3	0	0
T128	0	4	0	0
T129	0	7	0	0
T133	0	3	0	0
T134	0	4	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2182366	3864	0	0
T1	2394	13	0	0
T2	1267	3	0	0
T3	1530	5	0	0
T4	1397	3	0	0
T5	2798	14	0	0
T6	1024	3	0	0
T7	1336	5	0	0
T8	2521	3	0	0
T9	1478	6	0	0
T10	2572	5	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2182366	3914	0	0
T1	2394	14	0	0
T2	1267	3	0	0
T3	1530	5	0	0
T4	1397	3	0	0
T5	2798	14	0	0
T6	1024	3	0	0
T7	1336	5	0	0
T8	2521	3	0	0
T9	1478	6	0	0
T10	2572	5	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2182366	26926	0	0
T11	846	0	0	0
T12	15592	0	0	0
T15	2104	353	0	0
T16	1440	0	0	0
T26	0	13	0	0
T27	0	1449	0	0
T28	2951	0	0	0
T40	4717	0	0	0
T44	0	165	0	0
T49	3291	0	0	0
T50	1343	0	0	0
T51	1398	0	0	0
T53	1629	0	0	0
T137	0	3	0	0
T138	0	239	0	0
T139	0	625	0	0
T140	0	1090	0	0
T141	0	244	0	0
T142	0	611	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2182366	16465	0	0
T11	846	0	0	0
T12	15592	0	0	0
T15	2104	108	0	0
T16	1440	0	0	0
T27	0	763	0	0
T28	2951	0	0	0
T40	4717	0	0	0
T44	0	26	0	0
T49	3291	0	0	0
T50	1343	0	0	0
T51	1398	0	0	0
T53	1629	0	0	0
T138	0	53	0	0
T139	0	319	0	0
T140	0	836	0	0
T141	0	69	0	0
T142	0	421	0	0
T143	0	83	0	0
T144	0	26	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2182366	1999327	0	0
T1	2394	1494	0	0
T2	1267	1170	0	0
T3	1530	1448	0	0
T4	1397	1298	0	0
T5	2798	2700	0	0
T6	1024	953	0	0
T7	1336	980	0	0
T8	2521	2337	0	0
T9	1478	1047	0	0
T10	2572	2176	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2182366	29442	0	0
T11	846	0	0	0
T12	15592	0	0	0
T15	2104	43	0	0
T16	1440	0	0	0
T26	0	236	0	0
T27	0	97	0	0
T28	2951	0	0	0
T40	4717	0	0	0
T44	0	355	0	0
T49	3291	0	0	0
T50	1343	0	0	0
T51	1398	0	0	0
T53	1629	0	0	0
T137	0	261	0	0
T138	0	142	0	0
T139	0	1061	0	0
T140	0	2080	0	0
T141	0	36	0	0
T142	0	1279	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2182366	994	0	0
T1	2394	6	0	0
T2	1267	0	0	0
T3	1530	0	0	0
T4	1397	0	0	0
T5	2798	0	0	0
T6	1024	0	0	0
T7	1336	0	0	0
T8	2521	1	0	0
T9	1478	0	0	0
T10	2572	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T15	0	4	0	0
T28	0	4	0	0
T40	0	9	0	0
T45	0	1	0	0
T49	0	5	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2182366	140	0	0
T18	9654	20	0	0
T19	0	40	0	0
T20	0	20	0	0
T29	0	40	0	0
T30	0	20	0	0
T31	4866	0	0	0
T32	844	0	0	0
T33	1365	0	0	0
T34	2166	0	0	0
T35	7729	0	0	0
T36	2317	0	0	0
T37	2809	0	0	0
T38	5805	0	0	0
T39	15182	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2182366	994	0	0
T1	2394	6	0	0
T2	1267	0	0	0
T3	1530	0	0	0
T4	1397	0	0	0
T5	2798	0	0	0
T6	1024	0	0	0
T7	1336	0	0	0
T8	2521	1	0	0
T9	1478	0	0	0
T10	2572	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T15	0	4	0	0
T28	0	4	0	0
T40	0	9	0	0
T45	0	1	0	0
T49	0	5	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2182366	46536	0	0
T1	2394	48	0	0
T2	1267	0	0	0
T3	1530	0	0	0
T4	1397	0	0	0
T5	2798	0	0	0
T6	1024	0	0	0
T7	1336	0	0	0
T8	2521	0	0	0
T9	1478	28	0	0
T10	2572	0	0	0
T15	0	206	0	0
T16	0	27	0	0
T26	0	61	0	0
T27	0	743	0	0
T28	0	66	0	0
T40	0	462	0	0
T41	0	121	0	0
T47	0	22	0	0